Fig. 1. Overview of the rapid prototyping process.

Fig. 2. Code modules used to build the real-time program using makefile.

Fig. 3. Internal block diagram of the TMS320C6000 processor [8].

Fig. 4. The process and tools for mapping DSP kernels onto TMS320C6701 DSP.

Fig. 5. Reservation table B, CRT for II=2, 3 and 7.

Fig. 6. Reduced MS-state diagram for CRT (reservation table B) with II=7.

Fig. 7. CRT for II=7 with three initiations at time steps 0, 1 and 4 (represent by X, Y and Z) using latency sequence {1,3}.

Fig. 8. Overview of loop scheduling for TMS320C6701 DSP.

Fig. 9. Direct form FIR filter (a) DG for two loops, (b) Functional unit allocation requirement for two loops, (c) MIT for two iterations of loop, (d) CRT for II=6, (e) CRT for II=6 with modulo scheduling, (f) CRT for II=8 and (g) CRT for II=8 with modulo scheduling. (* indicates a cross-path from A- to B-sides or vice versa. A, B, C and D represent four initiations with time steps at 0, 2, 4 and 6.)

Fig. 10. Reduced state diagram for direct form FIR filter with II=8.

Fig. 11. Benchmarking of FIR filter as a block.

Fig. 12. Benchmarking of the IIR filter as a block.

Fig. 13. Benchmarking of the IIR filter as a block.

Fig. 14. Benchmarking of FFT blockset.

Table 1. Register requirement for direct form FIR filter based on DG in Fig. 9(a)

Table 2. FIR filter blockset performance in instruction cycles

Table 3. IIR filter blockset performance in instruction cycles

Table 4. Adaptive LMS filter blockset performance in instruction cycles

Table 5. Radix-2 DIT FFT blockset performance in instruction cycles