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doi:10.1016/S0026-2714(03)00038-6 
Copyright © 2003 Elsevier Science Ltd. All rights reserved.
Hot carrier degradation behavior in SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET) measured by gated-diode configuration*1
Received 25 July 2002;
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Abstract
In this paper the hot carrier degradation behavior of the SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET’s) is investigated based on the forward gated-diode configuration. With peak diode current as an indicator, the hot carrier induced degradation of SOI n-DTMOSFET’s is compared with the corresponding SOI nMOSFET’s. Due to the connection of the gate and the body and thus the positive-biased source–body and drain–body junction, the SOI n-DTMOSFET’s exhibit lower peak diode current than the conventional counterparts, showing smaller generated defect density and thus lower hot carrier induced degradation. The generated defect distribution in SOI n-DTMOSFET is analyzed. It is shown that despite of the tied gate-body, the peak of the generated defect density tends to lie in the gate-to-drain overlap region. The defect distribution exerts different influences on the diode current of the long channel device and short channel device with different electric field. Moreover, even with the positive biased body, the generated defects in SOI DTMOSFT are more apt to flow to front interface rather than back interface, resulting in the more severe degradation of the front interface in SOI n-DTMOSFET’s. This gives the main flow direction of the generated defects.
