In order to design a fault tolerant digital system, it is necessary to understand its behavior with the presence of faults in early design stage. Fault simulation is a process to purposely inject faults into a software circuit model and observe its faulty behavior. However, such simulation’s runtime tends to grow exponentially when test circuit becomes large. FPGA-based fault emulation, which is fault simulation implemented in FPGA, is an efficient way to accelerate fault simulation process. This paper introduces a novel FPGA-based switch-level fault emulation system utilizing module-based dynamic partial reconfiguration. In this approach, faults are modeled at switch-level and mapped to gate-level description for efficient FPGA implementation. The circuit under test is partitioned using unbalanced partitioning structure so that faults are injected only in a small sub-circuit. Using module-based dynamic partial reconfiguration, faulty circuit partition can be downloaded to FPGA without erasing the fault-free part of the circuit. The resulting system’s runtime increases linearly with circuit size, therefore indicating high efficiency of this system when emulating large and complex circuits.