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Microelectronics Journal
Volume 34, Issue 11, November 2003, Pages 1019-1024
IEEE Workshop on Embedded System Codesign (ESCODES)
 
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doi:10.1016/S0026-2692(03)00170-8    How to Cite or Link Using DOI (Opens New Window)
Copyright © 2003 Elsevier Ltd. All rights reserved.

Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems

Jun Cheol ParkCorresponding Author Contact Information, E-mail The Corresponding Author, Vincent Mooney and Sudarshan K. Srinivasan

School of Electrical and Computer Engineering, Georgia Institute of Technology, 777 Atlantic Drive, Atlanta, GA 30332-0250, USA

Accepted 4 May 2003. ;
Available online 12 July 2003.

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Abstract

In this paper we show that the energy reductions obtained from using two techniques, data remapping (DR) and voltage/frequency scaling of off-chip bus and memory, combine to provide interesting trade offs between energy, execution time and power. Both methods aim to reduce the energy consumed by the memory subsystem. DR is a fully automatic compile time technique applicable to pointer-intensive dynamic applications. Voltage/frequency scaling of off-chip memory is a technique applied at the hardware level. When combined together, energy reductions can be as high as 49.45%. The improvements are verified in the context of three OLDEN pointer-centric benchmarks, namely Perimeter, Health and TSP.

Author Keywords: Low power; Embedded systems; Energy model; Voltage/frequency scaling; Compiler optimizations

Article Outline

1. Introduction
2. Related work
3. Experimental setup
4. Data remapping
5. Voltage and frequency scaling of off-chip memory and buses
6. Design space exploration
7. Results
8. Conclusion
Acknowledgements
References





Microelectronics Journal
Volume 34, Issue 11, November 2003, Pages 1019-1024
IEEE Workshop on Embedded System Codesign (ESCODES)
 
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