Copyright © 2003 Elsevier Ltd. All rights reserved.
Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems
Accepted 4 May 2003. ;
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Abstract
In this paper we show that the energy reductions obtained from using two techniques, data remapping (DR) and voltage/frequency scaling of off-chip bus and memory, combine to provide interesting trade offs between energy, execution time and power. Both methods aim to reduce the energy consumed by the memory subsystem. DR is a fully automatic compile time technique applicable to pointer-intensive dynamic applications. Voltage/frequency scaling of off-chip memory is a technique applied at the hardware level. When combined together, energy reductions can be as high as 49.45%. The improvements are verified in the context of three OLDEN pointer-centric benchmarks, namely Perimeter, Health and TSP.
Author Keywords: Low power; Embedded systems; Energy model; Voltage/frequency scaling; Compiler optimizations






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