doi:10.1016/S0026-2692(03)00160-5 
Copyright © 2003 Elsevier Ltd. All rights reserved.
Testing analog circuits using spectral analysis
Instituto de Informática-PPGC, Universidade Federal do Rio Grande do Sul—UFRGS, Av. Bento Gonçalves, 9500, Bloco IV - Prédio 43412, Porto Alegre RS CEP 91501-970, Brazil
Received 16 November 2002;
accepted 9 April 2003. ;
Available online 12 July 2003.
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Abstract
In this work a test strategy for analog circuits based on spectral analysis is proposed. The test strategy is blind, in the sense that only statistical information about the input signal is needed, but no sampling of the input signal is required. This feature allows the test of analog circuits with minimum analog hardware addition. In the context of Systems-on-Chip, this strategy needs only the inclusion of a small random signal generator, and transfers most of the signal processing to the digital domain, allowing the use of a purely digital tester or a digital BIST technique. This paper presents the underlying principle of the method and experimental test results for linear analog systems.
Author Keywords: Mixed-signal BIST; DSP-based test
Fig. 1. System-on-Chip (SOC) example showing an analog block.
Fig. 2. Test strategy using power spectral density (PSD) estimation (top: training phase; bottom: testing phase).
Fig. 3. True PSD (·), theoretical error (dark lines) and 100 PSD estimates (light lines) using Welch's method [
11] with 0% overlap and hanning window (MATLAB simulation).
Fig. 4. (a) The theoretical PSD for a fault-free system and faulty system, showing the normalized error expected, and (b) the same figure, with the overlapped PSD region marked.
Fig. 5. The theoretical PSD for a fault-free system and faulty system showing the difference between the estimated PSD and the reference PSD (‘A’), and the difference between the error limit for the reference PSD and the reference PSD itself (‘B’).
Fig. 6. Schematic diagram of the biquad filter.
Fig. 7. Test for capacitor C1 and record lengths of 12,800 (‘×’) and 51,200 (‘·’) samples: (a) results for parameter par_mean, and (b) results for parameter par_sum.
Fig. 8. Test for capacitor C1 with a reduced comparison threshold: (a) results for parameter par_mean and (b) results for parameter par_sum.
Fig. 9. Test for capacitor C1 with a 70% reduction in the comparison threshold: (a) results for parameter par_mean and (b) results for parameter par_sum.
Fig. 10. Distance measures for changes in C1 from −90, −50, −20, 0, 20, 50 and 90% and threshold for 20% error in PSD estimates.
Fig. 11. Distance measures for changes in C1 from −99 to +99%, using noise as input signal and PSD estimates. (a) Estimates using 12,800 points and (b) estimates using 51,200 points.
Fig. 12. Experimental setup.
Table 1. PSD distance measured for 20% error in the PSD estimates (12,800 points, threshold: 1.5×107)
Values in bold indicate no fault detected.
Table 2. PSD distance measured for 20% error in the PSD estimates (12,800 points, threshold: 1.8×107)
Values in bold indicate no fault detected.
Abstract
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