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doi:10.1016/0167-9260(93)90049-I 
Copyright © 1993 Published by Elsevier Science B.V.
Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
Received 27 February 1992;
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Abstract
Patterns of faults occuring at strategic locations may render an entire VLSI system unusable regardless of its component redundancy and of its reconfiguration capabilities. The characterization of such patterns is obviously crucial for the identification, testing and detection of catastrophic events. The fault patterns that are catastrophic for regular architectures, particularly the systolic arrays, have been extensively studied. For a given link configuration, there are many fault patterns which are catastrophic. Among those, there is a particular fault pattern, called the reference fault pattern, which is crucial for the development of testing techniques; furthermore, the efficiency of any testing algorithm can be further improved in the presence of efficient algorithms for constructing the reference fault pattern. In this paper, we establish several new properties of catostrophic fault patterns: based on these properties, as well as the existing ones, we develop a new algorithm for the construction of the reference fault pattern. The complexity of the new algorithm is O(kg) which is a significant improvement over the existing O(g2) algorithm, where k is the number of bypass links, and g is the length of the largest bypass link.
Author Keywords: Systolic arrays; reconfiguration; catastrophic fault patterns
