Copyright © 1993 Published by Elsevier Science B. V.
A study of the resetability of synchronous sequential circuits
Available online 14 August 2003.
Abstract
The resetability of synchronous sequential circuits is investigated through an improved three-value simulation-based algorithm and a parallel synchronizing-tree method. It is shown that many standard benchmarks can be reset using one of these two methodologies, including some circuits which cannot be analyzed by current BDD-based symbolic algorithms.






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