Copyright © 1993 Published by Elsevier Science B. V.
Session A5: VLSI design. Chairman: Antonio Núñez
An empirical model to estimate power consumption in GaAs DCFL/SDCFL circuits
Available online 14 August 2003.
Abstract
Power dissipation is a conflicting criterium for designing high performance VLSI GaAs circuits. This paper describes a power formulation to estimate the consumption in SDCFL/DCFL circuits. It uses polynomial expressions in order to fit the power values measured with HSPICE. Besides these expressions are suitable for incorporation into an optimization strategy. The agreement with measured results is excellent, with error less than 10% over the tested cases.
Author Keywords: VLSI Power Estimation; CAD; GaAs DCFL/SDCFL; Optimization






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