Fault simulation constitutes an indispensable tool in ensuring the correctness and quality of manufactured digital designs. Traditional uniprocessor based algorithms for fault simulation have been observed to be agonizingly slow for today's large and complex digital designs. More recently, a few researchers introduce an approach, as evident in the literature, wherein the fault set is partitioned and the digital design fault simulated for each of the fault subset on separate processors of a parallel processor system. The approach is limited in that it continues to utilize the traditional uniprocessor-based algorithm and the performance results are not encouraging. This paper introduces, perhaps for the first time, a distributed algorithm that is capable of fault simulating both combinational and asynchronous sequential digital designs on parallel processors. An underlying assumption of the algorithm is that the digital design, under fault simulation, is partitioned by the user. In this approach, referred to as NODIFS in this paper, every component in the circuit is modeled as an asynchronous, concurrent, entity that is fault simulated as soon as appropriate signal transitions and fault lists are asserted at its input ports. The circuit partitioning is such that components of every partition are allocated to a unique processor of the parallel processor system. Consequently, a number of components may be concurrently fault simulated on multiple processors in NODIFS implying significant increase in throughput. This approach promises (i) very high throughput because of its ability, in principle, to utilize the maximal inherent parallelism, and (ii) scalability. The algorithm is novel in that the overall task of decision-making i.e., fault simulation of the circuit, is distributed into a number of natural, independent, and concurrent entities that execute asynchronously to utilize maximal parallelism. NODIFS's success is the result of the asynchronous distributed discrete-event simulation algorithm, YADDES, and a new approach to fault simulation. The notion of scalability implies that where the problem size increases, the algorithm continues to apply and, by increasing the number of computational engines proportionately, the performance of the algorithm will continue to increase. Furthermore, NODIFS is a natural choice for fault simulation of digital designs at the behavior-level — an eventual reality, wherein the ratio of the computational to communication load for the behavior models may approach a significantly large value. This paper also reports on an implementation of NODIFS on both the ARMSTRONG parallel processor system at Brown University and the performance results indicate significant increase in the speedup for a few representative example digital designs. It is stressed that the representative digital designs serve to support the mathematical validity of the algorithm along with the proof of correctness and not to demonstrate a high-performance, commercial, industrial-quality fault simulator.