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doi:10.1016/0165-6074(89)90270-6 
Copyright © 1989 Published by Elsevier Science B. V.
Expressing logical and temporal conditions in simulation environments: TPDL*
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Gianpiero Cabodi1, Paolo Camurati2, Paolo Prinetto3 and Matteo Sonza Reorda4
Available online 14 August 2003.
Abstract
TPDL* (Extended Temporal Profile Description Language), a general purpose language to express logical and temporal conditions, is the subject of this paper. The main features discussed are: the time model of TPDL*, its types and primitives, its use in a hierarchical, mixed-mode, concurrent fault simulation environment, and its verification by means of CONLAN. Examples are presented and the current implementation of the software tools supporting TPDL* is described.
Author Keywords: Temporal domain; Time model; Mixed mode simulation; Concurrent simulation; Conditioned command language; Assertion specification
Article Outline
1 Gianpiero Cabodi is currently a research adjoint with the Dept. of Computer Science and Automation at the Politecnico di Torino. He received the MS degree in electronic engineering in 1984, from 1985 to 1988 he has been a Ph D student with that institute. G. Cabodi's interests include CAD for VLSI, in particular logic and fault simulation, hardware acceleration, testing, and ATPG.
2 Paolo Camurati is currently a research adjoint with the Dept. of Computer Science and Automation at the Politecnico di Torino. He received the MS degree in electronic engineering in 1984, from 1985 to 1988 he has been a Ph D student with that institute. P. Camurati's interests include CAD for VLSI, in particular hardware description languages, design for testability, testing and ATPG, formal verification, and application of Al techniques to CAD, CAT, and CAR.
3 Paolo Prinetto is currently a full professor at the University of Udine (Italy). He received the MS degree in electronic engineering from the Politecnico di Torino in 1976. Since 1978 he has been assistant professor and since 1982 researcher at the Dept. of Computer Science and Automation at the Politecnico di Torino. He is a member of the IFIP Working Group 10.2. P. Prinetto's interests include CAD for VLSI, in particular hardware description languages, design for testability, testing and ATPG, formal verification of hardware correctness, and microprogramming.
4 Matteo Sonza Reorda received the M.S. degree in electronic engineering from the Politecnico di Torino in 1986. He is currently a Ph D student with the Dept. of Computer Science and Automation at the Politecnico di Torino. His interests include logic and fault simulation, random testing and probabilistic testability measures, and parallel processing.
