In this article we propose constraint based test generation as a new method for Automatic Test Pattern Generation (ATPG) in digital circuits, and describe a framework which makes it possible to uniquely handle a set of problems in currently existing ATPG methods, like the question of functional circuit modelling or the topological parallelization of the ATPG algorithm. The stated constructs (object oriented data-flow networks, the internal representation of network elements by dynamic binary constraint networks, the use of arc consistency algorithms, careful scheduling and a special dependency directed backtracking scheme) result in a high representational power and fast operating speed. Main concepts and reasons for decisions are shown before the details of a system architecture is presented.