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doi:10.1016/0165-6074(88)90077-4 
Copyright © 1988 Published by Elsevier Science B. V.
Let's design asynchronous VLSI systems*1
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Zebo Peng
Available online 14 August 2003.
Abstract
This paper discusses the impact of VLSI technology upon architecture consideration in respect to system timing. The problem inherited in the traditional synchronous timing strategy with the scaling down of feature size and scaling up of chip area is analyzed. An asynchronous timing approach is proposed where a set of independent clocks are used to synchronize different isochronous regions of a system but communication between isochronous regions are carried out asynchronously. The advantages of utilizing such an asynchronous timing approach in the VLSI environment is then given. Finally, a design methodology for the synthesis of asynchronous VLSI systems is described.
Article Outline
*1 This work was supported in part by the Swedish National Board for Technical Development (STU).
