Multi-valued circuits in fault detection of binary logic circuits

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Abstract

The paper considers two possibilities of employing multi-valued logic circuits for testing of binary networks. The first augments binary synchronous sequential machines through the addition of permutation inputs with multi-valued outputs. The second embeds binary combinational networks into easily testable ternary ones. Both approaches result in simplified testing procedures.

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This work was supported in part by the National Research Council of Canada grant number A-5280.

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