Elsevier

Computer-Aided Design

Volume 27, Issue 1, January 1995, Pages 65-74
Computer-Aided Design

Research
Performance-directed compaction for VLSI symbolic layouts

https://doi.org/10.1016/0010-4485(95)90754-4Get rights and content

Abstract

An effective approach for circuit performance improvement in VLSI symbolic layout compaction is presented. The approach is different from traditional approaches which aim at minimizing the total wire length; it directly optimizes the length of critical synchronous paths. Moreover, the critical synchronous paths are optimized before the layout size is minimized. The problem is so complicated that graph-theoretical algorithms for the general compaction problem cannot be used. Therefore, a new algorithm which consists of a graph-based technique and the simplex algorithm is proposed for the problem. Experimental results show that this algorithm is quite efficient.

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