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Investigation of different inputs and a new release policy in the proposed simulation model for wafer fabrication system

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Abstract

This paper investigates the effect of different inputs on selected performance metrics such as cycle time, WIP level and throughput in the processes of semiconductor wafer fab by developing a simulation model of representative but fictitious semiconductor wafer fab. The different inputs include arrival rate, arrival distribution, processing time, maintenance schedule, operator schedule, batch size, dispatching rule and release policy. Simulation results show that the relationship between inputs and system performance metrics, considered in this study, are extremely complex particularly for the inputs maintenance schedule, operator schedule and batch size. An overall result shows that dispatching rule and closed loop release policy can significamtly improve the performance of wafer fabrication system. However; major improvement comes from closed loop release policy. Accordingly, this paper presents a new closed loop release policy called as constant batch machine workload (CONSTBWL) to improve the performance of wafer fab. The behaviour of CONSTBWL is analysed in combination with dispatching rules using the proposed simulation model for wafer fab. Simulation results show that CONSTBWL policy outperformed traditional release policies in terms of the average cycle time, the work in process (WIP) level and the standard deviation of WIP level under a prescribed throughput level. Furthermore, the analysis of the results indicated that a good shop floor performance can be achieved with a right combination of closed loop release policy and simple dispatching rules with respect to the choice of performance metrics.

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  1. Department of Management Studies, Indian Institute of Science, Bangalore, 560012, India

    Rashmi Singh & M Mathirajan

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  1. Rashmi Singh
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  2. M Mathirajan
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Correspondence to Rashmi Singh.

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Singh, R., Mathirajan, M. Investigation of different inputs and a new release policy in the proposed simulation model for wafer fabrication system. Sādhanā 44, 41 (2019). https://doi.org/10.1007/s12046-018-1006-8

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  • DOI: https://doi.org/10.1007/s12046-018-1006-8

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