A 0.9 V, 4.57 mW UWB LNA with Improved Gain and Low Power Consumption for 3.1–10.6 GHz Ultra-Wide Band Applications

Abstract

In this paper, we present a 0.9 V, 4.57 mW UWB LNA with improved gain and low power consumption for 3.1–10.6 GHz ultra-wide band applications. In its input stage, a common gate amplifier is used to achieve approximately $50\,\Omega$ input resistance across the entire band, instead of using a common source stage. However, the current reused technique is used to save power consumption by using the same DC current path for both transistors in the designed circuit instead of utilizing two stage cascade configuration. The output matching is achieved by tuning the total parasitic capacitance with the inductor $\hbox {L}_{d1}$ at the output node. In its inter stage, inter stage matching technique is used to make the flat gain response and to extend the bandwidth, simultaneously. From simulation results, the designed LNA shows an average power gain $\hbox {S}_{21}$ of 15.8  dB with the gain variation of $\pm 0.97 \hbox { dB}$, an input return loss $\hbox {S}_{11}$ of −30 to −10 dB, a high reverse isolation $\hbox {S}_{12}$ of −59 to −43 dB, output return loss $\hbox {S}_{22}$ of −16 to −10 dB, and a small group-delay variation of $\pm 34$ ps across the entire band. It also shows minimum achievable noise figure below 3.2 dB, and a power consumption of 4.57 mW from a supply voltage of 0.9 V. When a two tone test is performed at 8 GHz with 10 MHz spacing, the linearity of the designed LNA such as 1-dB compression point and third order input intercept point are −22.5 and −9 dBm, respectively.