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Hardware Implementation of Successive-Cancellation Decoders for Polar Codes

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Abstract

The recently-discovered polar codes are seen as a major breakthrough in coding theory; they provably achieve the theoretical capacity of discrete memoryless channels using the low-complexity successive cancellation decoding algorithm. Motivated by recent developments in polar coding theory, we propose a family of efficient hardware implementations for successive cancellation (SC) polar decoders. We show that such decoders can be implemented with O(N) processing elements and O(N) memory elements. Furthermore, we show that SC decoding can be implemented in the logarithmic domain, thereby eliminating costly multiplication and division operations, and reducing the complexity of each processing element greatly. We also present a detailed architecture for an SC decoder and provide logic synthesis results confirming the linear complexity growth of the decoder as the code length increases.

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Notes

  1. Binary-coded integers are assumed to be stored in little-endian format.

  2. Nominal supply voltage and temperature are V dd  = 0.9 V and T = 125°C, respectively.

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Authors and Affiliations

  1. Institut Polytechnique de Bordeaux, Bordeaux, France

    Camille Leroux

  2. McGill University, 3480 University Street, Montreal, QC, Canada, H3A 0E9

    Alexandre J. Raymond, Gabi Sarkis & Warren J. Gross

  3. University of California San Diego, La Jolla, CA, USA

    Ido Tal & Alexander Vardy

Authors
  1. Camille Leroux
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  2. Alexandre J. Raymond
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  3. Gabi Sarkis
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  4. Ido Tal
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  5. Alexander Vardy
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  6. Warren J. Gross
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Corresponding author

Correspondence to Warren J. Gross.

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Leroux, C., Raymond, A.J., Sarkis, G. et al. Hardware Implementation of Successive-Cancellation Decoders for Polar Codes. J Sign Process Syst 69, 305–315 (2012). https://doi.org/10.1007/s11265-012-0685-3

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  • DOI: https://doi.org/10.1007/s11265-012-0685-3

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