Skip to main content
SpringerLink
Log in

Improving WCET by applying worst-case path optimizations

  • Published:
Real-Time Systems Aims and scope Submit manuscript

Abstract

It is advantageous to perform compiler optimizations that attempt to lower the worst-case execution time (WCET) of an embedded application since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compiler writers in recent years have used profile information to detect the frequently executed paths in a program and there has been considerable effort to develop compiler optimizations to improve these paths in order to reduce the average-case execution time (ACET). In this paper, we describe an approach to reduce the WCET by adapting and applying optimizations designed for frequent paths to the worst-case (WC) paths in an application. Instead of profiling to find the frequent paths, our WCET path optimization uses feedback from a timing analyzer to detect the WC paths in a function. Since these path-based optimizations may increase code size, the subsequent effects on the WCET due to these optimizations are measured to ensure that the worst-case path optimizations actually improve the WCET before committing to a code size increase. We evaluate these WC path optimizations and present results showing the decrease in WCET versus the increase in code size.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  • Arnold R, Mueller F, Whalley D (1994) Bounding worst-case instruction cache performance. In: Proceedings of the Fifteenth IEEE Real-time Systems Symposium. IEEE Computer Society Press, San Juan, Puerto Rico, pp 172–181

  • Benitez M (1994) Retargetable register allocation. PhD thesis, University of Virginia, Charlottesville, VA

  • Benitez ME, Davidson JW (1988) A portable global optimizer and linker. In: Proceedings of the SIGPLAN’;88 conference on Programming Language Design and Implementation. ACM Press, Atlanta, Georgia, pp 329–338

  • Benitez ME, Davidson JW (1994) The advantages of machine-dependent global optimization. In: Proceedings of the 1994 International Conference on Programming Languages and Architectures, pp 105–124

  • Eyre J, Bier J (1998) Dsp processors hit the mainsteam. IEEE Computer 31(8):51–59

    Google Scholar 

  • Fisher J (1981) Trace scheduling: A technique for global microcode commpaction. IEEE Transactions on Computers 30(7):478–490

    Google Scholar 

  • Gupta R, Berson D, Fang J (1997) Path profile guided partial dead code elimination using prediction. In: Proceedings of the International Conference on Parallel Architecture and Compilation Techniques. ACM Press, San Francisco, California, pp 102–115

  • Harmon M, Baker T, Whalley D (1994) A retargetable technique for prediction execution time of code segments. Real-Time Systems, pp 159–182

  • Healy C, Arnold R, Mueller F, Whalley D, Harmon M (1999a) Bounding pipeline and instruction cache performance. IEEE Transactions on Computers 48(1):53–70

    Article  Google Scholar 

  • Healy C, Sjodin M, Rustagi V, Whalley D, Van Engelen R (2000) Supporting timing analysis by automatic bounding of loop iterations. Real-Time Systems 18(2):121–148

    Article  Google Scholar 

  • Healy C, Whalley D (1999) Tighter timing predictions by automatic detection and exploitation of value-dependent constraints. In: Proceedings of the IEEE Real-Time Technology and Applications Symposium. IEEE Computer Society Press, Vancouver, Canada, pp 79–99

  • Healy C, Whalley D (2002) Automatic detection and exploitation of branch constraints for timing analysis. IEEE Transactions on Software Engineering 28(8):763–781

    Article  Google Scholar 

  • Healy C, Whalley D, Harmon M (1995) Integrating the timing analysis of pipelining and instruction caching. In: Proceedings of the Sixteenth IEEE Real-time Systems Symposium. IEEE Computer Society Press, Pisa, Italy, pp 288–297

  • Healy C, Whalley D, van Engelen R (1999b) A general approach for tight timing predictions of non-rectangular loops. In: WIP Proceedings of the IEEE Real-Time Technology and Applications Symposium. IEEE Computer Society Press, Vancouver, CA, pp 11–14

  • Hong S, Gerber R (1993) Compiling real-time programs into schedulable code. In: Proceedings of the SIGPLAN’;93. ACM Press, Albuquerque, New Mexico, pp 166–176

  • Hwu W, Mahlke S, Chen W, Change P, Warter N, Ouellette RBR, Hank R, Kiyohara T, Haab G, Holm J, Lavery D (1993) The superblock: An effective technique for vliw and superscalar compilation. Journal of Supercomputing 7(1):229–248

    Article  Google Scholar 

  • Ko L, A-Y N, Healy C, Ratliff E, Arnold R, Whalley D, Harmon M (1999) Timing constraint specification and analysis. Software Practice & Experience 29(1):77–98

    Article  Google Scholar 

  • Ko L, Healy C, Ratliff E, Arnold R, Whalley D, Harmon M (1996) Supporting the specification and analysis of timing constraints. In: Proceedings of the IEEE Real-Time Technology and Application Symposium. IEEE Computer Society Press, Boston, Massachusetts, pp 170–178

  • Kulkarni P, Zhao W, Moon H, Cho K, Whalley D, Davidson J, Bailey M, Paek Y, Gallivan K (2003) Finding effective optimization phase sequences. In: ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems. ACM Press, San Diego, California, pp 12–23

  • Lee S, Lee J, Park C, Min S (2004) A flexible tradeoff between code size and wcet using a dual instruction set processor. In: International Workshop on Software and Compilers for Embedded Systems, Springer, Amsterdam, Netherlands, 244–258

  • Mueller F (1997) Timing predictions for multi-level caches. In: ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-time Systems. ACM Press, Las Vegas, Nevada, pp 29–36

  • Mueller F (2000) Timing analysis for instruction caches. Real-Time Systems 18(2):209–239

    Article  Google Scholar 

  • Mueller F, Whalley D (1992) Avoiding unconditional jumps by code replication. In: Proceedings of the SIGPLAN ’92 Conference on Programming Languages Design and Implementation. ACM Press, San Francisco, California, pp 322–330

  • Mueller F, Whalley D. (1995) Avoiding conditional branches by code replication. In: Proceedings of the SIGPLAN ’95 Conference on Programming Languages Design and Implementation. ACM Press, La Jolla, California, pp 55–56

  • Star Core I (2001a) Sc100 simulator reference manual

  • Star Core I (2001b) Sc110 dsp core reference manual

  • Marlowe TSM (1992) Safe optimization for hard real-time programming. In: Special Session on Real-Time Programming, Second International Conference on Systems Integration, pp 438–446

  • White R, Mueller F, Healy C, Whalley D, Harmon M (1999) Timing analysis for data caches and wrap-around-fill caches. Real-Time Systems 17(1):209–233

    Article  Google Scholar 

  • White RT, Mueller F, Healy C, Whalley D, Harmon M (1997) Timing analysis for data caches and set-associative caches. In: Proceedings of the IEEE Real-Time Technology and Application Symposium. IEEE Computer Society Press, Montreal, Canada, pp 192–202

  • Zhao W, Cai B, Whalley D, Bailey M, Engelen R, Yuan X, Hiser J, Davidson J, Gallivan K, Jones D (2002) Vista: A system for interactive code improvement. In: ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems, ACM Press, Berlin, Germany, pp 155–164

  • Zhao W, Kulkarni P, Whalley D, Healy C, Mueller F, Uh G (2004) Tuning the wcet of embedded applications. In: Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium. IEEE Computer Society, Toronto, Canada, pp 472–480

  • Zhao W, Whalley D, Healy C, Mueller F (2004) Wcet code positioning. In: Proceedings of the IEEE Real-Time Systems Symposium. IEEE Computer Society, Lisbon, Portugal, pp 81–91

  • Zhao W, Whalley D, Healy C, Mueller F (2005) Improving wcet by applying a wc code positioning optimization. ACM Transactions on Architecture and Code Optimization, pp 335–365

Download references

Author information

Authors and Affiliations

  1. Computer Science Department, Florida State University, USA

    Wankang Zhao & David Whalley

  2. Department of Mathematics and Computer Science, Western Carolina University, USA

    William Kreahling

  3. Computer Science Department, Furman University, Greenville

    Christopher Healy

  4. Computer Science Department, North Carolina State University, USA

    Frank Mueller

Authors
  1. Wankang Zhao
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. William Kreahling
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. David Whalley
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Christopher Healy
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Frank Mueller
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to David Whalley.

Additional information

A preliminary version of this paper entitled “Improving WCET by optimizing worst-case paths” appeared in the 2005 Real-Time and Embedded Technology and Applications Symposium.

Wankang Zhao received his PhD in Computer Science from Florida State University in 2005. He was an associate professor in Nanjin University of Post and Telecommunications. He is currently working for Datamaxx Corporation.

William Kreahling received his PhD in Computer Science from Florida State University in 2005. He is currently an assistant professor in the Math and Computer Science department at Western Carolina University. His research interests include compilers, computer architecture and parallel computing.

David Whalley received his PhD in CS from the University of Virginia in 1990. He is currently the E.P. Miles professor and chair of the Computer Science department at Florida State University. His research interests include low-level compiler optimizations, tools for supporting the development and maintenance of compilers, program performance evaluation tools, predicting execution time, computer architecture, and embedded systems. Some of the techniques that he developed for new compiler optimizations and diagnostic tools are currently being applied in industrial and academic compilers. His research is currently supported by the National Science Foundation. More information about his background and research can be found on his home page, http://www.cs.fsu.edu/∼whalley. Dr. Whalley is a member of the IEEE Computer Society and the Association for Computing Machinery.

Chris Healy earned a PhD in computer science from Florida State University in 1999, and is currently an associate professor of computer science at Furman University. His research interests include static and parametric timing analysis, real-time and embedded systems, compilers and computer architecture. He is committed to research experiences for undergraduate students, and his work has been supported by funding from the National Science Foundation. He is a member of ACM and the IEEE Computer Society.

Frank Mueller is an Associate Professor in Computer Science and a member of the Centers for Embedded Systems Research (CESR) and High Performance Simulations (CHiPS) at North Carolina State University. Previously, he held positions at Lawrence Livermore National Laboratory and Humboldt University Berlin, Germany. He received his Ph.D. from Florida State University in 1994. He has published papers in the areas of embedded and real-time systems, compilers and parallel and distributed systems. He is a founding member of the ACM SIGBED board and the steering committee chair of the ACM SIGPLAN LCTES conference. He is a member of the ACM, ACM SIGPLAN, ACM SIGBED and the IEEE Computer Society. He is a recipient of an NSF Career Award.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Zhao, W., Kreahling, W., Whalley, D. et al. Improving WCET by applying worst-case path optimizations. Real-Time Syst 34, 129–152 (2006). https://doi.org/10.1007/s11241-006-8643-4

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11241-006-8643-4

Keywords

Search

Navigation