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Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations

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Abstract

In order to meet superior performance metrics along with denser logic integration and device miniaturization, FPGAs have become more susceptible to transistor related aging, coupled with manufacturing defects owing to increased complexity in photolithographic techniques, thereby reducing the reliability and lifetime. In this paper, we propose certain built-in circuit techniques that are integrated with the original design, to localize the source of any hard or soft errors, if any, with tolerable penalty in performance, against acceptable time and/or hardware redundancy. Circuit realization on FPGA has been achieved through primitive instantiation and constrained placement, such that the exact location from which the fault has emanated can be traced, and bypassed for mapping any subsequent logic on the same FPGA. The adopted design paradigm which had earlier proved its potential for high performance FPGA based designs, has now been adopted to facilitate fault localization.

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Authors and Affiliations

  1. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India

    Ayan Palchaudhuri & Anindya Sundar Dhar

Authors
  1. Ayan Palchaudhuri
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  2. Anindya Sundar Dhar
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Correspondence to Ayan Palchaudhuri.

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Responsible Editor: M. B. Tahoori

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Palchaudhuri, A., Dhar, A.S. Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations. J Electron Test 33, 529–537 (2017). https://doi.org/10.1007/s10836-017-5671-z

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  • DOI: https://doi.org/10.1007/s10836-017-5671-z

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