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Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

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Abstract

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics.

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Acknowledgments

This work has been supported in part by projects EU FP7 CP BASTION,  H2020 RIA IMMORTAL and H2020 TWINN TUTORIAL, by CNPq (Science and Technology Foundation, Brazil) under contract n. 303701/2011-0 (PQ) and FAPERGS/CAPES under contract n. 014/2012.

Authors would like to acknowledge Dr. Christoph Werner, from TU Munich, Germany for valuable comments regarding the proposed approach.

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Authors and Affiliations

  1. Department of Computer Engineering, Tallinn University of Technology, Akadeemia 15A, Tallinn, 12618, Estonia

    Maksim Jenihhin, Valentin Tihhomirov, Sergei Kostin, Jaan Raik & Raimund Ubar

  2. Politecnico di Torino, Department of Control and Computer Engineering, Corso Duca degli Abruzzi, 24, Torino, 10129, Italy

    Giovanni Squillero, Marco Gaudesi & Matteo Sonza Reorda

  3. Catholic University – PUCRS, Av. Ipiranga, 6681, Porto Alegre, 90619-900, Brazil

    Thiago Santos Copetti, Fabian Vargas, Leticia Bolzani Poehls & Guilherme Cardoso Medeiros

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  1. Maksim Jenihhin
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  2. Giovanni Squillero
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Correspondence to Maksim Jenihhin.

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Jenihhin, M., Squillero, G., Copetti, T.S. et al. Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J Electron Test 32, 273–289 (2016). https://doi.org/10.1007/s10836-016-5589-x

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