Abstract
This paper presents a new hybrid fault-tolerant architecture for robustness improvement of digital CMOS circuits and systems. It targets all kinds of errors in combinational part of logic circuits and thus, can be combined with advanced SEU protection techniques for sequential elements while reducing the power consumption. The proposed architecture combines different types of redundancies: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error correction. Moreover, it uses a pseudo-dynamic comparator for SET and timing errors detection. Besides, the proposed method also aims to reduce power consumption of fault-tolerant architectures while keeping a comparable area overhead compared to existing solutions. Results on the largest ISCAS’85 and ITC’99 benchmark circuits show that our approach has an area cost of about 3 % to 6 % with a power consumption saving of about 33 % compared to TMR architectures.
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Responsible Editor: N. A. Touba
This paper is an extended version of previously published papers. Main contributions of this paper with respect to [12, 15] are:
• Integration of the pseudo-dynamic comparator proposed in [15] in the hybrid fault tolerant architecture
• A complete implementation of the initial solution proposed in [12] with respect to timing constraints.
• A complete analysis of the hybrid fault tolerant architecture in terms of power consumption and silicon area.
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Tran, D.A., Virazel, A., Bosio, A. et al. A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J Electron Test 30, 401–413 (2014). https://doi.org/10.1007/s10836-014-5459-3
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DOI: https://doi.org/10.1007/s10836-014-5459-3