Skip to main content
SpringerLink
Log in

Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Drastic device shrinking, power supply reduction, increasing complexity and increasing operating speeds affect adversely the reliability of nowadays Integrate Circuits (ICs). In many modern designs, embedded memories occupy the largest part of the die and comprise the large majority of transistors. Furthermore, memories are designed as tight as allowed by the process, and are therefore more prone to failures than other circuits. Error correcting codes (ECCs) are an efficient mean for protecting memories against failures. A major drawback of ECCs is the speed penalty induced by the encoding and decoding circuits. In this paper, we present an architecture enabling implementing ECCs without speed penalty. Furthermore, as the manual implementation of this solution is impractical for complex System-on-Chips (SoCs), we propose an algorithm and a set of generic rules allowing automatic insertion of the delay-free ECCs in any complex architecture at Register Transfer Level (RTL). With respect to a naive insertion in the design of the new architecture, the algorithm enable up to 20 % hardware reduction. The Finite State Machines (FSM) that controls the new ECC architecture is also generated automatically. Experimental evaluations show that the hardware overhead of the speed penalty free ECCs protected memory compared to a standard implementation of ECC protected memory is about 2.5 % with an additional power consumption of 6 %.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Baeg S, Wen S, Wong R (2009) SRAM interleaving distance selection with a soft error failure model. IEEE Trans Nucl Sci 56(4):2111–2118

    Article  Google Scholar 

  2. Bajura MA, Boulghassoul Y, Naseer R, DasGupta S, Witulski AF, Sondeen J, Stansberry SD, Draper J, Massengill LW, Damoulakis JN (2007) Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs. IEEE Trans Nucl Sci 54(4):935–945

    Article  Google Scholar 

  3. Baumann R (2005) Soft errors in advanced computer systems. IEEE Des Test Comput 22(3):258–266

    Article  Google Scholar 

  4. Baumann RC (2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans Device Mater Reliab 5(3):305–316

    Article  MathSciNet  Google Scholar 

  5. Blum DR, Delgado-Frias JG (2007) Hardened by design techniques for implementing multiple-bit upset tolerant static memories, Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 2786–2789, 27–30 May 2007

  6. Bonnoit T, Nicolaidis M, Zergainoh N (2011) Towards a tool for implementing delay-free ECC in embedded memories, Computer Design (ICCD), 2011 IEEE 29th International Conference on, pp. 441–442, 9–12 Oct. 2011

  7. Bose RC, Shrikhande SS, Parker ET (1960) Further results on the construction of mutually orthogonal Latin squares and the falsity of Euler’s conjecture. Canad J Math 12:189–203

    Article  MathSciNet  MATH  Google Scholar 

  8. Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43(6):2874–2878

    Article  Google Scholar 

  9. Chang L, Montoye RK, Nakamura Y, Batson KA, Eickemeyer RJ, Dennard RH, Haensch W, Jamsek D (2008) An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches. IEEE J Solid State Circuits 43(4):956–963

    Article  Google Scholar 

  10. Chang J, Rusu S, Shoemaker J, Tam S, Huang M, Haque M, Chiu S, Truong K, Karim M, Leong G, Desai K, Goe R, Kulkarni S (2005) A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. IEEE J Solid State Circuits 40(1):195–203

    Article  Google Scholar 

  11. Chen S-K, Fuchs WK (2001) Compiler-assisted multiple instruction word retry for VLIW architectures. IEEE Trans Parallel Distrib Syst 12(12):1293–1304

    Article  Google Scholar 

  12. Chen CL, Hsiao MY (1984) Error-correcting codes for semiconductor memory applications: a state-of-the-art review. IBM J Res Dev 28(2):124–134

    Article  Google Scholar 

  13. Chishti Z, Alameldeen AR, Wilkerson C, Wu W, Lu S-L (2009) Improving cache lifetime reliability at ultra-low voltages. Micro’09, December 12–16, 2009, New York, NY, USA

  14. Datta R, Touba NA (2010) Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches, Test Conference (ITC), 2010 IEEE International, pp. 1–7, 2–4 Nov. 2010

  15. Dixit A, Wood A (2011) The impact of new technology on soft error rates, Reliability Physics Symposium (IRPS), 2011 IEEE International, pp. 5B.4.1–5B.4.7, 10–14 April 2011

  16. Ghosh S, Basu S, Touba NA (2005) Selecting error correcting codes to minimize power in memory checker circuits. J Low Power Electronics 1:63–72

    Article  Google Scholar 

  17. Gray K (2000) Adding error-correcting circuitry to ASIC memory. IEEE Spectr 37(4):55–60

    Article  Google Scholar 

  18. Hsiao MY (1970) A class of optimal minimum odd-weight-column SEC-DED codes. IBM J Res Dev 14(4):395–401

    Article  Google Scholar 

  19. Ibe E, Chung SS, Wen S, Yamaguchi H, Yahagi Y, Kameyama H, Yamamoto S, Akioka T (2006) Spreading diversity in multi-cell neutron-induced upsets with device scaling, Custom Integrated Circuits Conference, 2006. CICC ’06. IEEE, pp. 437–444, 10–13 Sept. 2006

  20. Ibe E, Taniguchi H, Yahagi Y, Shimbo K-i, Toba T (2010) Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule. IEEE Trans Electron Devices 57(7):1527–1538

    Article  Google Scholar 

  21. ITRS: International Technology Roadmap for Semiconductors. In Systedminrivers, 2009. http://www.itrs.net

  22. Jahinuzzaman SM, Shah JS, Rennie DJ, Sachdev M (2009) Design and analysis of A 5.3-pJ 64-kb gated ground SRAM with multiword ECC. IEEE J Solid State Circuits 44(9):2543–2553

    Article  Google Scholar 

  23. JEDEC (2006) Measurement and reporting of alpha particles and terrestrial cosmic ray-induced soft errors in semiconductor devices: JESD89A. JEDEC STANDARD, JEDEC Solid State Technology Association, pp. 1–85, No. 89

  24. Kawakami Y, Hane M, Nakamura H, Yamada T, Kumagai K (2004) Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation, Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 945–948, 13–15 Dec 2004

  25. Lee SE, Yang YS, Choi GS, Wu W, Iyer R (2011) Low-Power, Resilient Interconnection with Orthogonal Latin Squares. IEEE Des Test Comput 28(2):30–39

    Article  Google Scholar 

  26. Lin S, Kim Y-B, Lombardi F (2011) Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset, Computer Design (ICCD), 2011 IEEE 29th International Conference on, pp. 320–325, 9–12 Oct. 2011

  27. Maiz J, Hareland S, Zhang K, Armstrong P (2003) Characterization of multi-bit soft error events in advanced SRAMs, Electron Devices Meeting, 2003. IEDM ’03 Technical Digest. IEEE International, pp. 21.4.1–21.4.4, 8–10 Dec. 2003

  28. Meaney PJ, Swaney SB, Sanda PN, Spainhower L (2005) IBM z990 soft error detection and recovery. IEEE Trans Device Mater Reliab 5(3):419–427

    Article  Google Scholar 

  29. Metra C (2009) Trading off dependability and cost for nanoscale high performance microprocessors: the clock distribution problem. 2009 Workshop on Dependable and Secure Nanocomputing, June 29, 2009, Lisbon Portugal

  30. Muck M, Javaudin J-P (2005) Advanced OFDM modulators considered in the IST-WINNER framework for future wireless systems, 14th IST Mobile and Wireless Communications Submit

  31. Nicolaidis M, Bonnoit T, Zergainoh N-E (2011) Eliminating speed penalty in ECC protected memories, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1–6, 14–18 March 2011

  32. Ooi CY, Fujiwara H (2006) A new class of sequential circuits with acyclic test generation complexity, Computer Design, 2006. ICCD 2006. International Conference on, pp. 425–431, 1–4 Oct. 2007

  33. Radaelli D, Puchner H, Wong S, Daniel S (2005) Investigation of multi-bit upsets in a 150 nm technology SRAM device. IEEE Trans Nucl Sci 52(6):2433–2437

    Article  Google Scholar 

  34. Riedlinger RJ, Bhatia R, Biro L, Bowhill B, Fetzer E, Gronowski P, Grutkowski T (2011) A 32 nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, pp. 84–86, 20–24 Feb. 2011

  35. Sahnine C (2009) Architecture de circuit intégré reconfigurable, très haut débit et basse consommation pour le traitement numérique de l’OFDM avancé. Ph.D. dissertation, Grenoble INP, France

  36. Sahnine C, Javaudin J-P, Degoulet G, Jahan B (2007) OFDM/OQAM transceiver implementation, Design and Architectures for Signal and Image Processing (DASIP 2007), Grenoble, France, November 27–29, 2007

  37. Sinangil ME, Verma N, Chandrakasan AP (2009) A reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS. IEEE J Solid State Circuits 44(11):3163–3173

    Article  Google Scholar 

  38. Smith JE, Pleszkun AR (1988) Implementing precise interrupts in pipelined processors. IEEE Trans Comput 37(5):562–573

    Article  Google Scholar 

  39. Tosaka Y, Ehara H, Igeta M, Uemura T, Oka H, Matsuoka N, Hatanaka K (2004) Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology, Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International, pp. 941–944, 13–15 Dec. 2004

Download references

Author information

Authors and Affiliations

  1. Laboratoire TIMA, 46, avenue Félix Viallet, 38031, Grenoble Cedex, France

    Thierry Bonnoit, Michael Nicolaidis & Nacer-Eddine Zergainoh

Authors
  1. Thierry Bonnoit
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Michael Nicolaidis
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Nacer-Eddine Zergainoh
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Thierry Bonnoit.

Additional information

Responsible Editor: M. Violante

Rights and permissions

Reprints and permissions

About this article

Cite this article

Bonnoit, T., Nicolaidis, M. & Zergainoh, NE. Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study. J Electron Test 29, 383–400 (2013). https://doi.org/10.1007/s10836-013-5386-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-013-5386-8

Keywords

Search

Navigation