This issue of JETTA contains eight papers and one Letter. The topics covered are analog and mixed-signal test, digital circuit diagnosis, system test, power supply noise defects, test application, and testing of biochips. The third and fourth papers are derived from the program of IEEE European Test Symposium (ETS) of 2009 and 2010, respectively. Cecilia Metra once again deserves credit for editing of these papers.

Analog Test is the topic of first two papers. In the first paper, Xiaomei of North China Electric Power University, Beijing, China, and Xiaofeng and Guohua of Beihang University, Beijing, China, propose a Monte-Carlo method for simulation-based diagnosis of parametric and catastrophic faults. The second paper, authored by Ayadi, Masmoudi and Mahresi of National Engineering School of Sfax (ENIS), Sfax, Tunisia, discusses a built-in self-test and calibration technique for an RF circuit, a low noise amplifier.

A paper by Shukoor of Texas Instruments, Dallas, Texas, USA and Agrawal of Auburn University, Auburn, Alabama, USA discusses minimization of tests without reduction of their diagnostic capability. They define generalized independence with respect to a test set where two faults are considered independent if no test in the set can distinguish between them. This reduces the complexity of the integer linear program (ILP) used for test minimization. The ILP is further simplified by splitting into detection and diagnosis phases.

A software method for testing peripherals of a system is described in the next paper. The authors are Grosso, Sanchez, Sonza Reorda and Tonda from Politecnico di Torino, Torino, Italy, and Holguin and Medina from Universidad del Valle, Cali, and Universidad Pedagógica y Tecnológica de Colombia, Sogamoso, Colombia.

The next paper is authored by Ma of LSI Corporation, Milpitas, California, USA, Tehranipoor from University of Connecticut, Storrs, Connecticut, USA and Girard from Université de Montpellier II/CNRS, Montpellier Cedex 5, France. The paper gives a method for selecting tests that measure path delay while also increasing the delay through coupling from aggressor nets. Then a paper by Mauroux, Virazel, Bosio, Dilillo, Girard and Pravossoudovitch from Université de Montpellier II/CNRS, Montpellier Cedex 5, France and Godard, Festes and Vachez of ATMEL, Rousset Cedex, France establishes fault models for resistive defects in ATMEL eFlash memories. This paper is a generalization of previously reported work and is applicable to recent flash memory technologies.

A paper by Thibeault, Hariri and Hobeika from École de Technologie Supérieure, Montreal, QC, Canada proposes a new design for testability structure for delay fault testing. Sensors are inserted to capture selected data signals on which delay fault detection is desired. These sensors are clocked and capture any late transitions, which they then propagate to an observable output. The use of this sensor thus eliminates the capture cycle from a launch-on-shift test.

Among new types of micro-electromechanical systems (MEMS) that are evolving are microfluidic devices, which have clinical applications. A test for a fault consists of identifying a source reservoir that would supply a test droplet and then facilitating propagation of the droplet through a path containing the target fault to an observable point. The paper is authored by Zhao and Chakrabarty of Duke University, Durham, North Carolina, USA, and Bhattacharya of Indian Statistical Institute, Kolkata, India.

The final contribution is a JETTA Letter, authored by Kavithamani and Manikandan of Coimbatore Institute of Technology, Coimbatore, India, and Devarajan from Government College of Technology, Coimbatore, India. Authors suggest that parameters like driving point impedance, transfer impedance, voltage gain and current gain can detect component faults in analog circuits. The paper shows that measurement of input current, output voltage and output current can classify faulty circuits though the question of diagnosis must be answered by future research.