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IC Immunity Modeling Process Validation Using On-Chip Measurements

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Abstract

Developing integrated circuit (IC) immunity models and simulation flow has become one of the major concerns of ICs suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign cost. This paper presents an IC immunity modeling process including the standard immunity test applied to a dedicated test chip. An on-chip voltage sensor is used to characterize the radio frequency interference propagation inside the chip and thus validate the immunity modeling process.

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Acknowledgment

The authors would like to thank Freescale Semiconductor (Toulouse–France) and ESEO (Ecole supérieure d’Electronique de l’Ouest, ANGERS–France) for their technical support and their precious advices. This is supported by the national research agency (ANR JC).

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Authors and Affiliations

  1. CNRS, LAAS, University of Toulouse, INSA, 7 avenue du colonel Roche, F-31400, Toulouse, France

    S. Ben Dhia & A. Boyer

  2. Freescale Semiconductor, 134 avenue du General Eisenhower, 31023, Toulouse, France

    B. Vrignon & M. Deobarro

Authors
  1. S. Ben Dhia
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  2. A. Boyer
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  3. B. Vrignon
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  4. M. Deobarro
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Corresponding author

Correspondence to S. Ben Dhia.

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Responsible Editor: F. L. Vargas

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Ben Dhia, S., Boyer, A., Vrignon, B. et al. IC Immunity Modeling Process Validation Using On-Chip Measurements. J Electron Test 28, 339–348 (2012). https://doi.org/10.1007/s10836-012-5294-3

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  • DOI: https://doi.org/10.1007/s10836-012-5294-3

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