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Design of MAC unit for digital filters in signal processing and communication

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Abstract

Digital signal processors (DSP) the endless requirement is the development of ability in processors to hold the difficulties resulted in the assimilation of CPU cores in a particular IC. Certain functions like convolution, transform, correlation and filtering are performed using digital signal processor. All these functions requires multiplication and repetitive addition. So multiply and accumulate unit (MAC) has significance in digital signal processor. High performance processes are of high importance in the MAC unit. Finally DSP algorithms depend considerably on speed performance of MAC. In this paper, a high speed MAC unit based on Vedic multiplier(VM) technique is presented for Arithmetic Applications. The VM and the adder blocks in the MAC unit are designed using a high-speed Pipelined Brent Kung (BK) Adder architecture. The proposed design is compared with 32 bit MAC unit constructed using regular Brent Kung adder. It is observed from the synthesis results that proposed MAC unit is operating nearly five times quicker than MAC unit constructed using regular Brent Kung adder. All the designs were implemented on Xilinx Virtex 7 using Verilog HDL.

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Authors and Affiliations

  1. Vignan’s Foundation for Science Technology & Research, Guntur, India

    Basavoju Harish & M. S. S. Rukmini

  2. Kakatiya Institute of Technology & Science, Warangal, India

    K. Sivani

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  1. Basavoju Harish
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  2. M. S. S. Rukmini
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  3. K. Sivani
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Correspondence to Basavoju Harish.

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Harish, B., Rukmini, M.S.S. & Sivani, K. Design of MAC unit for digital filters in signal processing and communication. Int J Speech Technol 25, 561–565 (2022). https://doi.org/10.1007/s10772-021-09824-0

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  • DOI: https://doi.org/10.1007/s10772-021-09824-0

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