Abstract
Correct design of interface circuits is crucial for the development of System-on-Chips (SoC) using off-the-shelf IP cores. For correct operation, an interface circuit must meet strict synchronization timing constraints, and also respect sequencing constraints between events dictated by interfacing protocols and rational clock relations. In this paper, we propose a technique for automatically analyzing the interaction between independently specified synchronization constraints and sequencing constraints between events. We show how this analysis can be used to derive delay constraints for correct operation of interface circuits in a GALS system. Our methodology allows an SoC designer to mix and match different interfacing protocols, rational clock relations and synchronization constraints for communication between a pair of modules, and automatically explore their implications on correct interface circuit design.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Amon T, Borriello G, Hu T, Liu J (1997) Symbolic Timing Verification of Timing Diagrams using Presburger Formulas. In: Proc. of ACM/IEEE Design Automation Conference, pp. 226–231
Bagnara R., et al. PPL: The Parma Polyhedra Library.http://www.cs.unipr.it/ppl/
Burns SM (1991) Performance Analysis and Optimization of Asynchronous Circuits. Ph.D. thesis, California Institute of Technology
Chakraborty A, Greenstreet MR (2003) Efficient Self-Timed Interfaces for Crossing Clock Domains. In: Proc. of International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp. 78–88
Chakraborty S, Composing sequence diagrams for GALS systems.http://www.cse.iitb.ac.in/~supratik/tools/GALS_AutComp
Chakraborty S (1998) Polynomial-Time Techniques for Approximate Timing Analysis of Asynchronous Systems. Ph.D. thesis, Stanford University
Chaney TJ, Molnar CE (1973) Anomalous Behavior of Synchronizer and Arbiter Circuits. IEEE Trans Comput C-22(4): 421–422
Chapiro DM (1984) Globally Asynchronous Locally Synchronous Systems. Ph.D.thesis, Stanford University
Clariso R, Cortadella J (2004) Verification of Timed Circuits with Symbolic Delays. In: Proc. of Asia and South Pacific Design Automation Conference, pp. 226–231
Clarke EM, Grumberg O, Peled D (1999) Model checking. MIT Press
Dantzig GB, Eaves BC (1973) Fourier-Motzkin Elimination and its Dual. J Combinat Theory (A) 13:288–297
Fisler K (1999) Timing Diagrams: Formalization and Algorithmic Verification. J Logic, Lang Inform 8(3):323–361
Ginosar R, Kol R (1998) Adaptive synchronization. In: Proc. of Internanational Conf. Computer Design 188–189
Greenstreet MR (1993) STARI: A Technique for High-Bandwidth Communication. Ph.D.thesis, Princeton University
ITU-T (1996) Message Sequence Charts (MSC), Recommendation Z.120 Technical Report
Kessels J, Peeters A, Wielage P, Kim S-J (2002) Clock Synchronization through Handshake Signalling. In: Proc. of International Symposium on Advanced Research in Asynchronous Circuits and Systems pp 59–68
Khordoc K, Cerny E (1998) Semantics and Verification of Action Diagrams with Linear Timing Constraints. ACM Trans Design Autom Electr Syst 3:21–50
Mekie J, Chakraborty S, Sharma DK (2004) Evaluation of Pausible Clocking for Interfacing High-Speed IP Cores in GALS Systems. In: Proc. of International Conference on VLSI Design pp 559–564
Mekie J, Chakraborty S, Venkataramani G, Thiagarajan PS, Sharma DK (2006) Interface design for rationally clocked GALS systems. In: Proc. of International Symposium on Advanced Research in Asynchronous Circuits and Systems
Muttersbach J (2001) Globally Asynchronous Locally Synchronous Architechtures for VLSI Systems. Ph.D. thesis, ETH Zurich
Myers CJ, Meng TH-Y (2002) Synthesis of timed asynchronous circuits. IEEE Trans VLSI Syst 1(2):106–119
Pugh W, et al. The Omega project.http://www.cs.umd.edu/projects/omega
Rosenberger FU, Molnar CE, Chaney TJ, Fang T-P (1988) Q-Modules: Internally Clocked Delay-Insensitive Modules. IEEE Transactions on Computers C-37(9):1005–1018
Roychoudhury A, Thiagarajan PS, Tran T-A, Zvereva V (2004) Automatic Generation of Protocol Converters from Scenario-based Specifications. In: Proc. of IEEE International Real-Time Systems Symposium, pp. 447–458
Seitz CL (1980) System Timing. In: Mead CA, Conway LA (eds) Introduction to VLSI Systems, Addison-Wesley, Chap 7
Sjogren AE, Myers CJ (1999) Interfacing Synchronous and Asynchronous Modules within a High-speed Pipeline. IEEE Trans VLSI Syst 8(5):573–583
Sproull RF, Sutherland IE (1985) Stoppable clock. Sutherland, Sproull and Associates. Technical Memo 3438
Stucki MJ, Cox Jr JR (1979) Synchronization Strategies. In: Seitz CL (ed.). Proc. of the First Caltech Conference on Very Large Scale Integration, pp 375–393
Weste NHE, Eshraghian K (1992) Principles of CMOS VLSI design: A systems perspective. Addison-Wesley Publishing Company
Yen T-Y, Ishii A, Casavant A, Wolf W (1998) Efficient Algorithms for Interface Timing Verification. Formal Methods in Syst Design 12(3):241–265
Yun KY, Donohue RP (1996) Pausible clocking: A First Step Toward Heterogeneous systems. In: Proc. of International Conference on Computer Design, pp. 118–123
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Chakraborty, S., Mekie, J. & Sharma, D.K. Reasoning about synchronization in GALS systems. Form Method Syst Des 28, 153–169 (2006). https://doi.org/10.1007/s10703-006-7841-y
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10703-006-7841-y