Abstract
A highly energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the merge-and-split technique, which eliminates the need of the extra reference voltage (Vcm). The switching procedure is performed on the simple binary weighted capacitor arrays without any capacitor-splitting. Compared with the conventional scheme, the proposed switching scheme can achieve 98.45% saving in switching energy and 75% capacitors-area reduction. Besides, because two capacitor arrays are switched symmetrically, the common-mode voltage of capacitive digital-to-analog converter (CDAC) keeps constant until the LSB cycle. The proposed switching scheme is verified in a 0.6-V 10-bit 200-kS/s SAR ADC in 40 nm CMOS technology.
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Acknowledgments
This work was supported by the National Natural Science Foundation of China (No. 61871118), the Fundamental Research Funds for the Central Universities (No. 2242019k30037) and the Top-notch Academic Programs Project of Jiangsu Higher Education Institutions (TAPP) (No. PPZY2015B136).
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Li, J., Huang, L., Zhang, L. et al. Energy-efficient switching scheme for SAR ADCs using two reference levels. Analog Integr Circ Sig Process 106, 661–667 (2021). https://doi.org/10.1007/s10470-020-01787-7
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DOI: https://doi.org/10.1007/s10470-020-01787-7