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Evaluating nanomagnetic logic circuit layouts using different clock schemes

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Abstract

The complementary metal oxide semiconductor technology, CMOS, is reaching its physical limitations, as the transistors’ feature size decreases. A promising alternative is the nanomagnetic logic technology (NML), a paradigm of field-coupled nanocomputing. This technology applies single domain nanomagnets to implement digital logic with switching energies that are orders of magnitude lower than a CMOS transistor due to the complete absence of static energy dissipation. When designing nanomagnetic circuitry, several challenges arise, such as the design of a clocking system able to avoid signal disruption due to the thermal noise effect. In this paper, we compare four NML clocking schemes: BANCS, USE, RES, and 2DDWave by analyzing scalability and area overhead of combinational and sequential circuits.

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Authors and Affiliations

  1. Science and Technology Institute, Universidade Federal de Viçosa, Campus Florestal, Rodovia LMG 818, km 06., Florestal, MG, Brazil

    Ruan Evangelista Formigoni, Leandro Lázaro Araújo Vieira & José Augusto M. Nacif

  2. Universidade Federal de Minas Gerais, Av. Pres. Antônio Carlos, 6627 - Pampulha, Belo Horizonte, MG, 31270-901, Brazil

    Omar Paranaiba Vilela Neto

  3. Universidade Federal de Viçosa, Avenida Peter Henry Rolfs, s/n - Campus Universitário, Viçosa, MG, 36570-977, Brazil

    Ricardo Ferreira

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  1. Ruan Evangelista Formigoni
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Formigoni, R.E., Vieira, L.L.A., Neto, O.P.V. et al. Evaluating nanomagnetic logic circuit layouts using different clock schemes. Analog Integr Circ Sig Process 106, 205–218 (2021). https://doi.org/10.1007/s10470-020-01648-3

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