Abstract
A 6-Gbps dual-mode digital clock and data recovery (CDR) circuit for both the mesochronous clocking system and the plesiochronous clocking system has been developed. Fabricated in a 65-nm CMOS technology, the prototype consumes 25.2 and 22.8-mW from 1.2-V supply and root-mean-square jitter of the recovered clock was measured to be 7.2 and 8.5-ps for 6-Gbps mesochronous system and plesiochronous system, respectively. For both operation modes, less than 10−12 bit-error-rate was achieved with 27-1 pseudo-random binary sequence pattern and active area of the implemented CDR circuit is 0.025-mm2.
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References
Chen, S., Li, H., Yang, L., Yang, Z., Hu, W., and Chiang, P.-Y. (2013). A 1.2pJ/b 6.4 Gb/s 8 + 1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28 nm CMOS. In Proceedings of IEEE custom integrated circuits conference (pp. 1–4).
Yin, W., Inti, R., Elshazly, A., Talegaonkar, M., Young, B., & Hanumolu, P. (2011). A TDC-less 7 mW 2.5 Gb/s digital CDR with linear loop dynamics and offset-free data recovery. IEEE Journal of Solid-State Circuits, 46(12), 3163–3173.
Loh, M., & Emami-Neyestanak, A. (2012). A 3 × 9 Gb/s shared, all-digital CDR for high-speed, high-density I/O. IEEE Journal of Solid-State Circuits, 47(3), 641–651.
Pan, H., Valliappan, M., Zhang, W., Vakilian, K., Lee, S.-H., Hatamkhani, H., Caresosa, M., Khanoyan, K., Tong, H., Tran, D., Brewster, A., and Fujimori, I. (2011). A digital wideband CDR with ±15.6kppm frequency tracking at 8 Gb/s in 40 nm CMOS. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers (pp. 442–444).
Shu, G., Saxina, S., Choi, W.-S., Talegaonkar, M., Inti, R., Elshazly, A., et al. (2014). A reference-less clock and data recovery circuit using phase-rotating phase-locked loop. IEEE Journal of Solid-State Circuits, 49(4), 1036–1047.
Rodoni, L., Buren, G., Huber, A., Schmatz, M., & Jackel, H. (2009). A 5.75 to 44 Gb/s quarter rate CDR with data rate selection in 90 nm bulk CMOS. IEEE Journal of Solid-State Circuits, 44(7), 1927–1941.
Hanumolu, P., Wei, G.-Y., & Moon, U.-K. (2008). A wide-tracking range clock and data recovery circuit. IEEE Journal of Solid-State Circuits, 43(2), 425–439.
Larsson, P. (1999). A 2-1600-MHz CMOS clock recovery PLL with low-vdd capability. IEEE Journal of Solid-State Circuits, 34(12), 1951–1960.
Lee, W.-Y., Hwang, K.-D., & Kim, L.-S. (2012). A 5.4/2.7/1.62-Gb/s receiver for DisplayPort version 1.2 with multi-rate operation scheme. IEEE Transactions on Circuits and Systems-I, 59(12), 2858–2866.
High-definition multimedia interface (HDMI) Specification 2.0, HDMI Forum.
DisplayPort Specification 1.2, Video Equipment Standard Association (VESA).
Chen, M.-S., Hafez, A., & Yang, C.-K. (2013). A 0.1-1.5 GHz 8-bit inverter-based digital-to-phase converter using harmonic rejection. IEEE Journal of Solid-State Circuits, 48(11), 2681–2692.
Acknowledgments
This work was supported by the IT R&D program of MOTIE (Ministry of Trade, Industry and Energy) and KEIT (Korea Evaluation Institute of Industrial Technology) (No. 10044451, 4K UHD Level AV Signal Transmit SoC for Mobile Device) and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No. 2013R1A2A2A01004958). The CAD tools were provided by IC Design Education Center (IDEC), Korea.
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Jeon, MK., Yoo, C. A 6-Gbps dual-mode digital clock and data recovery circuit in a 65-nm CMOS technology. Analog Integr Circ Sig Process 85, 209–215 (2015). https://doi.org/10.1007/s10470-015-0613-0
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DOI: https://doi.org/10.1007/s10470-015-0613-0