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A size sensitivity method for interactive CMOS circuit sizing

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Abstract

A new device sizing method for CMOS analog integrated circuit is proposed. This method employs graphical sensitivity curves of certain performance metric with respect to device sizes, called size sensitivity, to guide the designer to choose proper device sizes semi-automatically. It is shown that the plot of sensitivity curves in the frequency-domain can exhibit quantitative performance dependence to device sizes nearby dominant pole/zero locations. For accurate sensitivity calculation, the dependence on dc sensitivity in the computation of ac sensitivity to device size is emphasized and an EKV model-based implementation is outlined. The proposed graphical semi-automatic analog sizing methodology differentiates itself from the traditional black-box approaches with which the user has no interference in the optimization process. An interactive semi-automatic analog sizing tool with a graphical interface allows the user to decide which device sizes are more rewarding to tune. An operational amplifier is sized by using the proposed interactive tool.

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References

  1. Alvarez, A. R., Abdi, B. L., Young, D. L., Weed, H. D., Teplik, J., & Herald, E. R. (1988). Application of statistical design and response surface methods to computer-aided VLSI device design. IEEE Transactions on Computer-Aided Design, 7(2), 272–288.

    Article  Google Scholar 

  2. Binkley, D. M. (2008). Tradeoffs and optimization in analog CMOS design. Wiley, New York.

    Book  Google Scholar 

  3. Binkley, D. M., Hopper, C. E., Tucker, S. D., Moss, B. C., Rochelle, J. M., & Foty, D. P. (2003). A CAD methodology for optimizing transistor current and sizing in analog CMOS design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(2), 225–237.

    Article  Google Scholar 

  4. Chen, J., Shi, G., Tai, A., & Lee, F. (2012). A size sensitivity method for interactive MOS circuit sizing. In Proceedings of 10th IEEE International NEWCAS Conference (pp. 169–172). Montreal, Canada.

  5. Daems, W., Gielen, G., & Sansen, W. (2003). Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(5), 514–537.

    Article  Google Scholar 

  6. Enz, C., Krummenachaer, F., & Vittoz, A. (1995) An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integrated Circuits and Signal Processing, Special issue: low-voltage low-power analog integrated circuits, 8(1), 83–114

    Article  Google Scholar 

  7. Enz, C. C., & Vittoz, E. A. (2006). Charge-based MOS transistor modeling the EKV model for low-power and RF IC design (1st ed.). Wiley, New York.

    Book  Google Scholar 

  8. Gielen, G. E., Walscharts, H., & Sansen, W. (1990). Analog circuit design optimization based on symbolic simulation and simulated annealing. IEEE Journal of Solid-State Circuit, 25(3), 707–713.

    Article  Google Scholar 

  9. Graeb, H. E. (2007). Analog design centering and sizing. Springer, Dordrecht, The Netherlands.

    Google Scholar 

  10. Hershenson, M., Boyd, S., & Lee, T. (2001) Optimal design of a CMOS op-amp via geometric programing. IEEE Transactions on Computer-Aided Design of Circuits and Systems, 20(1), 1–21

    Article  Google Scholar 

  11. Jespers, P. G. A. (2010). The gm/ID methodology, a sizing tool for low-voltage analog CMOS circuits. Springer, Heidelberg, Germany.

    Book  Google Scholar 

  12. Joshi, S. (2008). Large-scale geometric programming for devices and circuits. Ph.D. thesis, Department of Electrical Engineering, Stanford University.

  13. Lee, J. Y., Huang, X., & Rohrer, R. A. (1992). Pole and zero sensitivity calculation in asymptotic waveform evaluation. IEEE Transactions on Computer-Aided Design, 11(5), 586–597

    Article  Google Scholar 

  14. Li, X., Xu, H., Shi, G., & Tai, A. (2011). Hierarchical symbolic sensitivity computation with applications to large amplifier circuit design. In Proceedings of International Conference on Circuits and Systems (ISCAS) (pp. 2733–2736). Rio de Janeiro, Brazil.

  15. Ma, D., Shi, G., & Lee, A. (2010). A design platform for analog device size sensitivity analysis and visualization. In Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS) (pp. 48–51). Malaysia.

  16. Mandal, P., & Visvanathan, V. (2001). CMOS opamp sizing using a geometric programming formulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 20(1), 22–38

    Article  Google Scholar 

  17. Massier, T., Graeb, H., & Schlichtmann, U. (2008). The sizing rules method for CMOS and bipolar analog integrated circuit synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(12), 2209–2222

    Article  Google Scholar 

  18. McConaghy, T., & Gielen, G. G. E. (2009). Globally reliable variation-aware sizing of analog integrated circuits via response surfaces and structural homotopy. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(11), 1627–1640

    Article  Google Scholar 

  19. Medeiro, F., Fernandez, F. V., Dominquez-Castro, R., & Rodriguez-Vazquez, A. (1994). A statistical optimization based approach for automated sizing of analog cell. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (pp. 594–597).

  20. Mendhurwar, K., Sundani, H., Aggarwal, P., Raut R., & Devabhaktuni, V. (2012). A new approach to sizing analog CMOS building blocks using pre-compiled neural network models. Analog Integrated Circuits and Signal Processing 70,265–281

    Article  Google Scholar 

  21. Pillage, L. T., Rohrer, R. A., & Visweswariah, C. (1995). Electronic circuit and system simulation methods. McGraw-Hill, New York

    Google Scholar 

  22. Sarason, D. (2007). Complex function theory (2nd ed.). American Mathematical Society, Providence, RI.

    MATH  Google Scholar 

  23. Schwencker, R., Eckmueller, J., Graeb, H., & Antreich, K. (1999). Automating the sizing of analog CMOS circuits by consideration of structure constraints. In Proceedings of Design, Automation and Test in Europe (pp. 323–327). Munich, Germany.

  24. Shi, C. J. R., & Tan, X. D. (2000). Canonical symbolic analysis of large analog circuits with determinant decision diagrams. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19(1), 1–18

    Article  Google Scholar 

  25. Shi, G. (2013). Graph-pair decision diagram construction for topological symbolic circuit analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(2), 275–288

    Article  Google Scholar 

  26. Shi, G. (2013) A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits. Analog Integrated Circuits and Signal Processing , 74(2),331–343

    Article  Google Scholar 

  27. Shi, G., & Meng, X. (2009). Variational analog integrated circuit design by symbolic sensitivity analysis. In Proceedings of International Symposium on Circuits and Systems (ISCAS) (pp. 3002–3005). Taiwan, China.

  28. Silveira, F., Flandre, D., & Jespers, P. G. A. (1996). A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. IEEE Journal of Solid-State Circuits, 31(9),1314–1319

    Article  Google Scholar 

  29. Spence, R. (1999). The facilitation of insight for analog design. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 46(5),540–548

    Article  Google Scholar 

  30. Vlach, J., & Singhal, K. (1994). Computer methods for circuit analysis and design (2nd ed.). New York: Van Nostrand Reinhold Company. (Reprint 2003, Norwell, MA: Kluwer Academic Publishers).

  31. Wang, J. (2008). Response surface modeling for analog and mixed-signal design. Ph.D. thesis, Electrical and Computer Engineering, Carnegie Mellon University.

  32. Yang, H. (2006). Symbolic sensitivity analysis techniques and applications in analog circuit synthesis. Ph.D. thesis, Department of Electrical and Computer Engineering, University of Cincinnati, USA.

  33. Yang, H., Agarwal, A., & Vemuri, R. (2005). Fast analog circuit synthesis using multi-parameter sensitivity analysis based on element-coefficient diagrams. In Proceedings of IEEE Computer Society Annual Symposium on VLSI (pp. 71–76). Tampa, Florida, USA.

  34. Yang, H., Ranjan, M., Verhaegen, W., Ding, M., Vemuri, R., & Gielen, G. (2005). Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. In Proceedings of Asia South-Pacific Design Automation Conference (ASPDAC) (pp. 230–235). Yokohama, Japan.

  35. Zhang, H., & Shi, G. (2011). Symbolic behavioral modeling for slew and settling analysis of operational amplifiers. In Proceedings of IEEE 54th Midwest Symposium on Circuits and Systems (pp. 1–4). Seoul, South Korea.

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Acknowledgments

This research was supported in part by the National Natural Science Foundation of China (NSFC Grant No. 61176129) and by a research Grant from Synopsys, Inc. (2010–2013).

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Authors and Affiliations

  1. School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China

    Guoyong Shi & Jiajun Chen

  2. Synopsys, Inc., Mountain View, CA, 94043, USA

    Andy Tai & Frank Lee

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  1. Guoyong Shi
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  2. Jiajun Chen
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  4. Frank Lee
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Correspondence to Guoyong Shi.

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Shi, G., Chen, J., Tai, A. et al. A size sensitivity method for interactive CMOS circuit sizing. Analog Integr Circ Sig Process 77, 95–104 (2013). https://doi.org/10.1007/s10470-013-0143-6

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  • DOI: https://doi.org/10.1007/s10470-013-0143-6

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