Skip to main content
Log in

Performance evaluation of domino logic circuits for wide fan-in gates with FinFET

  • Technical Paper
  • Published:
Microsystem Technologies Aims and scope Submit manuscript

Abstract

Power dissipation, propagation delay and noise are major issues in digital circuit design. In this paper, a new leakage-tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant delay increment for 8 and 16 input OR gates are designed and simulated using existing and proposed techniques in FinFET technology. In this paper utilize the property of FinFET on domino circuit in order to improve the overall performance of the circuit. Here all the circuit is simulated at 32 nm process technology by using HSPICE simulation at supply voltage of 0.9 V in MOS, short gate (SG) and low power (LP) mode at 10 MHz frequency. Comparison is done on the basis of power dissipation, propagation delay and unity noise gain. FinFET technology in SG mode reduces propagation delay while LP mode reduces power dissipation. Maximum power saved by ultra low power stacked (ULP-ST) domino logic for 8 and 16 input OR at 15.5, 18.39% in SFLD, 32.91, 28.22% in HSD, 40.60, 44.67% in CKD in SG mode and for LP mode 18.26, 21.68% in SFLD, 28.84, 27.94% in HSD, 55.45, 44.59% in CKD, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  • Allah MW, Anis MH, Elmasry MI (2000) High speed dynamic logic circuits for scaled-down CMOS and MTCMOS technologies. In: Proceedings of IEEE international symposium low power electronics design

  • Chun JW, Roger Chen CY (2010) A novel leakage power reduction technique for CMOS circuit design. In: Proceedings of IEEE, pp 119–122

  • Dadoria AK, Khare K, Gupta TK, Singh RP (2016a) Ultra low power high speed domino logic circuit by using FiNFET technology. Adv Electr Electron Eng 14(1):66–74

    Google Scholar 

  • Dadoria AK, Khare K, Singh RP (2016b) Sleepy lector: a novel approach for leakage reduction in DSM technology. In: Proceedings of IEEE confluence 2016. Amity University, Noida, India

  • Dadoria AK, Khare K, Gupta TK, Singh RP (2017a) Ultra-low power FinFET-based domino circuits. Int J Electron 104:952–967

    Article  Google Scholar 

  • Dadoria AK, Khare K, Gupta TK, Khare N (2017b) Integrating sleep and pass transistor logic for leakage power reduction in FinFET circuits. J Comput Electron 16(3):867–874

    Article  Google Scholar 

  • Dadoria AK, Khare K, Gupta TK, Singh RP (2017c) Leakage reduction by using FinFET technique for nanoscale technology circuits. J Nanoelectron Optoelectron 12(3):1–8

    Article  Google Scholar 

  • Frustaci F, Corsonello P, Perri S, Cocorullo G (2008) High-performance noise-tolerant circuit techniques for CMOS dynamic logic. IET Circuits Devices Syst 2(6):537–548

    Article  Google Scholar 

  • Gong N, Guo B, Lou J, Wang J (2008) Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits. Microelectron J 39:1149–1155

    Article  Google Scholar 

  • Hisamoto D, Lee W-C, Kedzierski J, Takeuchi H, Asano K, Kuo C, Anderson E, King T-J, Bokor J, Hu C (2000) FinFET—a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans Electron Devices 47(12):2320–2325

    Article  Google Scholar 

  • Jeyasingh RGD, Bhat N (2008) A low power, process invariant keeper design for high speed dynamic logic circuits. In: Proceedings of ISCAS, pp 1668–1671

  • Liao N, Cui XX, Liao K, Ma KS, Wu D, Wei W, Li R, Yu DS (2014) Low power adiabatic logic based on FinFETs. Sci China 57:1–13 (ISSN: 022402:1-022402:13)

    Article  Google Scholar 

  • Lih Y, Tzartzanis N, Walker W (2007) A leakage current replica keeper for dynamic circuits. IEEE J Solid-State Circuits 42(1):48–55

    Article  Google Scholar 

  • Mahmoodi H, Roy K (2004) Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style. IEEE Trans Circuits Syst I Reg Pap 51(3):495–503

    Article  Google Scholar 

  • Nowak E et al (2004) Turning silicon on its edge. IEEE Circuits Device Mag 51(3):20–31

    Article  Google Scholar 

  • Peiravi A, Asyaei M (2012) Robust low leakage controlled keeper by current comparison domino for wide fan-in gates. Elsevier Integr VLSI J 45:22–32

    Article  Google Scholar 

  • Peiravi A, Asyaei M (2013) Current-comparison-based domino: new low-leakage high-speed domino circuit for wide fan-in gates. IEEE Trans Very Larg Scale Integr Syst 21(5):22–32

    Google Scholar 

  • Rasouli SH, Dadgour HF, Endo K, Koike H, Banerjee K (2010) Design optimization of FinFET domino logic considering the width quantization property. IEEE Trans Electro Devices 57(11):2934–2943

    Article  Google Scholar 

  • Tawfik SA, Kursun V (2008) Low-power and compact sequential circuits with independent-gats FinFETs. IEEE Trans Electro Devices 55(1):66–70

    Article  Google Scholar 

  • Tawfik SA, Kursun V (2009) FinFET domino logic with independent gate keepers. Elsevier Micro Electron J 41:1–10

    Google Scholar 

  • Wong H-SP, Frank DJ, Solomon PM, Wann CH-J, Welser JJ (1999) Nanoscale CMOS. Proc IEEE 87:537–570

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Ajay Kumar Dadoria.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Dadoria, A.K., Khare, K., Panwar, U. et al. Performance evaluation of domino logic circuits for wide fan-in gates with FinFET. Microsyst Technol 24, 3341–3348 (2018). https://doi.org/10.1007/s00542-017-3691-3

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00542-017-3691-3

Navigation