Abstract
Memory design is the most complex part of any electronic devices. There are many parameters either intrinsic or extrinsic effects the system. In the memory design some features should be focus like stability, leakage current and delay. These parameters play important role in terms of performance. There is a lot of degradation in performance while not using the system. In this paper we used MTCMOS tech for optimizing parameters like stability static power dissipation and delay. We characterized the parameters of conventional 6T, Asym8T Asym 9T. The main focus is on the Asym 9T because it had low static power dissipation low delay and high stability. We simulated Asym 9T on different values of the threshold values and β values. Asym 9T SRAM cell exhibits high stability with dual threshold voltage.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Chang L et al (2008) An 8T SRAM for variability tolerance and low-voltage operation in high-performance caches. IEEE J Solid State Circuits 43(4):959–963
Jain RK, Shah AP, Neema V (2017) A novel energy efficient high-speed 10-transistor full adder cell based on pass transistor logic. J Nanotechnol Optoelectron 12:1–6
Jiao H, Kursun V (2010) Ground-bouncing-noise-aware combinational MTCMOS circuits. IEEE Trans Circuits Syst I57(8):2053–2065
Jiao H, Kursun V (2011) Asymmetrical ground gating for low leakage and data robust sleep mode in memory banks. In: Proceedings of the IEEE international symposium on VLSI design, automation and test, pp 205–208
Jiao H, Kursun V (2012) Tri-mode operation for noise reduction and data preservation in low-leakage multi-threshold CMOS circuits. Book Chapter, VLSI-SoC: forward-looking trends in IC and systems design, pp 258–290
Jiao H, Kursun V (2013) Ground gated 8T SRAM cells with enhanced read and hold data stability. In: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp 52–57
Jiao H et al (2016) Low power and robust memory circuits with asymmetrical ground gating. Microelectron J 48:109–119
Liu Z, Kursun V (2008) Characterization of a novel nine transistor SRAM cell. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(4):488–492
Zhang K et al (2005) SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. IEEE J Solid State Circuits 40(4):895–901
Acknowledgements
We are thankful to M.P. Council of Science & Technology, Bhopal, India, for finical support under R&D project scheme. No: 1950/CST/R&D/Phy & Engg Sc/2015: 27th Aug 2015.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Tiwari, N., Atre, P., Parihar, P. et al. Highly robust asymmetrical 9T SRAM with trimode MTCOS technique. Microsyst Technol 25, 1593–1598 (2019). https://doi.org/10.1007/s00542-017-3434-5
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00542-017-3434-5