Skip to main content
SpringerLink
Log in

Realization of high-speed logic functions using heterojunction vertical TFET

  • Published:
Applied Physics A Aims and scope Submit manuscript

Abstract

In this paper, a dual-gate silicon–germanium heterojunction vertical TFET with germanium as the source material (HJ-VTFET) is proposed for realizing compact logic functions. A single device with both gate terminals is biased independently during 2D simulation to understand fundamental two-input Boolean gates (OR, NAND, AND and NOR). The vital element in attaining various logic functions using double-gate vertical TFET is deploying a gate–source connection with an appropriate choice of silicon body thickness. The OR and NAND gates are realized using n-type and p-type HJ-VTFETs, respectively, by applying an independent voltage at both gates. While the AND and NOR gates are realized using n-type and p-type HJ-VTFETs, respectively, employing the gate–source overlap method. These implementations show that an exclusive feature of TFETs, such as ambipolar conduction with tunneling dependent on gate–source overlapping, can be realized for logic functions. With such a compact implementation with HJ-VTFET, the present work revealed some serious problems, such as a large subthreshold swing (SS), a small ON-state current (\(I_\textrm{ON}\)), and high propagation delay (\(\tau _\textrm{D}\)). For AND functionality, in contrast to pure Si-based-VTFET (Si-VTFET), the HJ-VTFET raised \(I_\textrm{ON}\)/\(I_\textrm{OFF}\) via 3rd-order magnitude with around 67% improvement in SS. Further, an OR gate is realized with proposed HJ-VTFET and revealed less \(\tau _\textrm{D}\) around 0.012 nS, compared to the other gates realized using HJ-VTFET.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. L. Stanley, Hurst, VLSI Custom Microelectronics: Digital: Analog, and Mixed-Signal, 1st edn. (CRC Press, 1998). https://doi.org/10.1201/9780203909713

    Book  Google Scholar 

  2. D.-G. Park et al., Robust ternary metal gate electrodes for dual gate CMOS devices. In: International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), pp. 30.6.1–30.6.4 (2001), https://doi.org/10.1109/IEDM.2001.979597.

  3. I. Polishchuk, P. Ranade, T.-J. King, C. Hu, Dual work function metal gate CMOS transistors by Ni-Ti interdiffusion. IEEE Electron Device Lett. 23(4), 200–202 (2002). https://doi.org/10.1109/55.992838

    Article  ADS  Google Scholar 

  4. C.Y. Wong, J.Y. Sun, Y. Taur, C.S. Oh, R. Angelucci, B. Davari, Doping of n\(^{+}\) and p\(^{+}\) polysilicon in a dual-gate CMOS process. In: Technical Digest., International Electron Devices Meeting, pp. 238-241 (1988), https://doi.org/10.1109/IEDM.1988.32800.

  5. H. Lu, A. Seabaugh, Tunnel field-effect transistors: state-of-the-art. IEEE J. Electron Devices Soc. 2(4), 44–49 (2014). https://doi.org/10.1109/JEDS.2014.2326622

    Article  Google Scholar 

  6. K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high-\(\kappa \) gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007). https://doi.org/10.1109/TED.2007.899389

    Article  ADS  Google Scholar 

  7. T. Kitade, K. Ohkura, A. Nakajima, Room-temperature operation of an exclusive-OR circuit using a highly doped Si single-electron transistor. Appl. Phys. Lett. 86, 123118 (2005). https://doi.org/10.1063/1.1894594

    Article  ADS  Google Scholar 

  8. S.-M. Kang, Y. Leblebici, CMOS Digital Integrated Circuits Analysis & Design (McGraw-Hill, New York, 2002)

    Google Scholar 

  9. S. Mookerjea, R. Krishnan, S. Datta, V. Narayanan, Effective capacitance and drive current for tunnel FET (TFET) CV/I estimation. IEEE Trans. Electron Devices 56(9), 2092–2098 (2009). https://doi.org/10.1109/TED.2009.2026516

    Article  ADS  Google Scholar 

  10. S. Ahish, D. Sharma, Y.B. Nithin Kumar, M.H. Vasantha, Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using Gaussian doping. IEEE Trans. Electron Devices 63(1), 288–295 (2016). https://doi.org/10.1109/TED.2015.2503141

    Article  ADS  Google Scholar 

  11. L. Liu, D. Mohata, S. Datta, Scaling length theory of double-gate interband tunnel field-effect transistors. IEEE Trans. Electron Devices 59(4), 902–908 (2012). https://doi.org/10.1109/TED.2012.2183875

    Article  ADS  Google Scholar 

  12. W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans. Electron Devices 57(9), 2317–2319 (2010). https://doi.org/10.1109/TED.2010.2052167

    Article  ADS  Google Scholar 

  13. S.H. Kim, H. Kam, C. Hu, T.-J. K. Liu, Germanium-source tunnel field effect transistors with record high ION/IOFF. In: 2009 Symposium on VLSI Technology, pp. 178–179 (2009)

  14. S. Saurabh, M.J. Kumar, Estimation and compensation of process-induced variations in nanoscale tunnel field-effect transistors for improved reliability. IEEE Trans. Device Mater. Reliab. 10(3), 390–395 (2010). https://doi.org/10.1109/TDMR.2010.2054095

    Article  Google Scholar 

  15. S. Banerjee, S. Garg, S. Saurabh, Realizing logic functions using single double-gate tunnel FETs: a simulation study. IEEE Electron Device Lett. 39(5), 773–776 (2018). https://doi.org/10.1109/LED.2018.2819205

    Article  ADS  Google Scholar 

  16. S. Garg, S. Saurabh, Implementing logic functions using independently-controlled gate in double-gate tunnel FETs: investigation and analysis. IEEE Access 7, 117591–117599 (2019). https://doi.org/10.1109/ACCESS.2019.2936610

    Article  Google Scholar 

  17. A. Kamath et al., Realizing and and or functions with single vertical-slit field-effect transistor. IEEE Electron Device Lett. 33(2), 152–154 (2012). https://doi.org/10.1109/LED.2011.2176309

    Article  ADS  Google Scholar 

  18. G. Wadhwa, B. Raj, An analytical modeling of charge plasma based tunnel field effect transistor with impacts of gate underlap region. Superlattices Microstruct. 142, 106512 (2020). https://doi.org/10.1016/j.spmi.2020.106512

    Article  Google Scholar 

  19. J. Zhu et al., Design and simulation of a novel graded-channel heterojunction tunnel FET with high \({I} _{ riptscriptstyle\text{ ON }}/{I} _{ riptscriptstyle\text{ OFF }}\) ratio and steep swing. IEEE Electron Device Lett. 38(9), 1200–1203 (2017). https://doi.org/10.1109/LED.2017.2734679

    Article  ADS  Google Scholar 

  20. X. Duan, J. Zhang, S. Wang, Y. Li, S. Xu, Y. Hao, A high-performance gate engineered InGaN dopingless tunnel FET. IEEE Trans. Electron Devices 65(3), 1223–1229 (2018). https://doi.org/10.1109/TED.2018.2796848

    Article  ADS  Google Scholar 

  21. G. Isella, D. Chrastina, B. Rössner, T. Hackbarth, H.J. Herzog, U. König, H. von Känel, Low-energy plasma-enhanced chemical vapor deposition for strained Si and Ge heterostructures and devices. Solid-State Electron. 48(8), 1317–1323 (2004). https://doi.org/10.1016/j.sse.2004.01.013

    Article  ADS  Google Scholar 

  22. C.-Y. Wen, M.C. Reuter, J. Bruley, J. Tersoff, S. Kodambaka, E.A. Stach, F.M. Ross, Formation of compositionally abrupt axial heterojunctions in silicon-germanium nanowires. Science 326(5957), 1247–1250 (2009). https://doi.org/10.1126/science.1178606

    Article  ADS  Google Scholar 

  23. L. Chen, W.Y. Fung, W. Lu, Vertical nanowire heterojunction devices based on a clean Si/Ge interface. Nano Lett. 13(11), 5521–5527 (2013). https://doi.org/10.1021/nl403112a

    Article  ADS  Google Scholar 

  24. V. Ambekar, M. Panchore, Realization of Boolean functions using heterojunction tunnel FETs. Silicon (2022). https://doi.org/10.1007/s12633-022-01888-0

    Article  Google Scholar 

  25. Y. Khatami, K. Banerjee, Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits. IEEE Trans. Electron Devices 56(11), 2752–2761 (2009). https://doi.org/10.1109/TED.2009.2030831

    Article  ADS  Google Scholar 

  26. G. Wadhwa, J. Singh, B. Raj, Design and investigation of doped triple metal double gate vertical TFET for performance enhancement. Silicon 13, 1839–1849 (2021). https://doi.org/10.1007/s12633-020-00585-0

    Article  Google Scholar 

  27. Silvaco. Atlas users manual. [Online]. http://www.silvaco.com (2015)

  28. S. Saurabh, M.J. Kumar, Fundamentals of Tunnel Field-Effect Transistors, 1st edn. (CRC Press, 2016). https://doi.org/10.1201/9781315367354

    Book  Google Scholar 

  29. G. Wadhwa, B. Raj, Surface potential modeling and simulation analysis of dopingless TFET biosensor. Silicon 14, 2147–2156 (2022). https://doi.org/10.1007/s12633-021-01011-9

    Article  Google Scholar 

  30. F.S. Neves et al., Low-frequency noise analysis and modeling in vertical tunnel FETs with Ge source. IEEE Trans. Electron Devices 63(4), 1658–1665 (2016). https://doi.org/10.1109/TED.2016.2533360

    Article  ADS  MathSciNet  Google Scholar 

  31. T. Krishnamohan, D. Kim, C.D. Nguyen, C. Jungemann, Y. Nishi, K.C. Saraswat, High-mobility low band-to-band-tunneling strained-Germanium double-gate heterostructure FETs: Simulations. IEEE Trans. Electron Devices 53(5), 1000–1009 (2006). https://doi.org/10.1109/TED.2006.872367

    Article  ADS  Google Scholar 

  32. A. Theja, M. Panchore, Performance investigation of GaSb/Si heterojunction based gate underlap and overlap vertical TFET biosensor. IEEE Trans. NanoBiosci. (2022). https://doi.org/10.1109/TNB.2022.3183934

    Article  Google Scholar 

  33. M. Chiang, K. Kim, C. Chuang, C. Tretz, High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices. IEEE Trans. Electron Devices 53(9), 2370–2377 (2006). https://doi.org/10.1109/TED.2006.881052

    Article  ADS  Google Scholar 

  34. W.G. Vandenberghe, B. Sorée, W. Magnus, G. Groeseneken, M.V. Fischetti, Impact of field-induced quantum confinement in tunneling field-effect devices. Appl. Phys. Lett. 98, 143503 (2011). https://doi.org/10.1063/1.3573812

    Article  ADS  Google Scholar 

  35. D.B. Abdi, M. Jagadesh Kumar, Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain. IEEE J. Electron Devices Soc. 2(6), 187–190 (2014). https://doi.org/10.1109/JEDS.2014.2327626

    Article  Google Scholar 

  36. M. H. Na, E. J. Nowak, W. Haensch, J. Cai, The effective drive current in CMOS inverters. In: Digest. International Electron Devices Meeting, pp. 121–124 (2002), https://doi.org/10.1109/IEDM.2002.1175793.

  37. D. Esseni, M. Guglielmini, B. Kapidani, T. Rollo, M. Alioto, Tunnel FETs for ultralow voltage digital VLSI circuits: part i-device-circuit interaction and evaluation at device level. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(12), 2488–2498 (2014). https://doi.org/10.1109/TVLSI.2013.2293135

    Article  Google Scholar 

  38. Q.-T. Zhao et al., Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications. IEEE Journal of the Electron Devices Society 3(3), 103–114 (2015). https://doi.org/10.1109/JEDS.2015.2400371

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Patna, Bihar, 800005, India

    Vikas Ambekar & Meena Panchore

Authors
  1. Vikas Ambekar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Meena Panchore
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vikas Ambekar.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Ambekar, V., Panchore, M. Realization of high-speed logic functions using heterojunction vertical TFET. Appl. Phys. A 129, 166 (2023). https://doi.org/10.1007/s00339-023-06419-1

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s00339-023-06419-1

Keywords

Search

Navigation