Abstract
The test technique called “boundary scan test” (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.
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References
JTAG, Final Version 2.0 of the standard Boundary Scan Architecture, April 1988.
F. Beenker, K. Eerdewijk, R. Gerritsen, F. Peacock, and M. Star, “Macro testing: Unifying IC and board test,” IEEE Design and Test, December 1986, pp. 26–32.
R. van Riessen, H. Kerkhoff, and A. Kloppenburg, “Design and implementation of a hierarchical testable architecture using the boundary scan standard,” Proc. 1st European Test Conf., 1989, pp. 112–118.
L. Wang, M. Marhoefer, and E. McCluskey, “A self-test and self-diagnosis architecture for boards using boundary scan,” Proc. 1st European Test Conf., 1989, pp. 119–126.
Factron-Schlumberger, “The primer of high-performance incircuit testing,” 1985.
P. Wagner, “Interconnect testing with boundary scan,” Proc. 18th Inter. Test. Conf., 1987, pp. 52–57.
A. Hassan, J. Rajski, and V. Agarwal, “Testing and diagnosis of interconnects using boundary scan architecture,” Proc. 19th Inter. Test Conf., 1988, pp. 126–137.
W. Kautz, “Testing of faults in wiring networks,” IEEE Trans. Comput., C-23(4): 358–363, April 1974.
J. Hayes, “Fault Modeling,” IEEE Design and Test, April 1985, pp. 88–95.
Texas Instruments, “A primer on testability—test and emulation,” 1989.
R. Bennetts, “Introduction to digital board testing,” Crane Russak & Company, Inc., 1982 (ISBN 0-8449-1385-0).
H. Fujiwara, “On the acceleration of test generation algorithms,” IEEE Trans. Comput., C-32(12): 1137–1144, 1983.
T. Kirkland, and M. Mercer, “Algorithms for automatic test pattern generation,” IEEE Design and Test, June 1988, pp. 43–55.
S. Vining, “Tradeoff decisions made for a P1149.1 controller design,” Proc. 20th Inter. Test Conf., 1989, pp. 47–54.
F. Francese, “Il collaudo di circuiti su piastra stampata,” Alta Frequenza, 57(6): 177–187, 1988.
F. de Jong, “Test pattern generation for boards with partial Boundary Scan Test.” (Paper under preparation.)
P. Goel and M.T. McMahon, “Electronic chip-in-place test,” Proc. 13th Inter. Test Conf., 1982, pp. 83–90.
IEEE/P1149.1 Working Group, IEEE Std. 1149.1-1990 Standard Test Access Port and Boundary-Scan Architecture, February 1990.
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De Jong, F., Matos, J.S. & Ferreira, J.M. Boundary scan test, test methodology, and fault modeling. J Electron Test 2, 77–88 (1991). https://doi.org/10.1007/BF00134944
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DOI: https://doi.org/10.1007/BF00134944