Abstract
A data path verifier for register transfer level is presented in this paper. The verifier checks if all the operations and the data transfers in a behavioral description can be realized on a given data path without any scheduling conflicts. Temporal logic based language Tokio is adopted as a behavioral description language in this verifier. In Tokio, designers can directly describe concurrent behaviors controlled by more than one finite state machine without unfolding parallelism. The verifier checks for the consistency between a behavior and a structure automatically and lightens the load of designers. The actual LSI chip which consists of 18,000 gates on CMOS gate array has been successfully verified. This verifier is concluded to have the ability to verify practical hardware design.
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References
T. Aoyagi, M. Fujita, and T. Moto-oka. Temporal Logic Programming Language Tokio. In Logic Programming Conference '85, pages 128–137, Springer-Verlag, 1985.
M. Fujita, S. Kono, H. Tanaka, and T. Moto-oka. Aid to Hierarchical and Structured Logic Design Using Temporal Logic and Prolog. In IEE Proceedings, Vol.133, Pt.E, pages 283–294, IEE, 1986.
H. Koike and H. Tanaka. Multi-Context Procesing and Data Balancing Mechanism of the Parallel Inference Machine PIE64. In Fifth Generation Computer Systems, pages 970–977, ICOT, 1988.
S. Kono, T. Aoyagi, M. Fujita, and H. Tanaka. Implementation of Temporal Logic Programming Language Tokio. In Logic Programming Conference '85, pages 138–147, Springer-Verlag, 1985.
M.C. McFarland, A.C. Parker, and R. Camposano. Tutorial on High-Level Synthesis. In 25th Design Automation Conference, pages 330–336, ACM/IEEE, 1988.
B. Moszkowski. A Temporal Logic for Multi-Level Reasoning about Hardware. In CHDL '83, IFIP, 1983.
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© 1991 Springer-Verlag Berlin Heidelberg
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Nakamura, H., Kukimoto, Y., Fujita, M., Tanaka, H. (1991). A data path verifier for register transfer level using temporal logic language Tokio. In: Clarke, E.M., Kurshan, R.P. (eds) Computer-Aided Verification. CAV 1990. Lecture Notes in Computer Science, vol 531. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0023721
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DOI: https://doi.org/10.1007/BFb0023721
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