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Highly parallel inference engine PIE —Goal rewriting model and machine architecture—

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Abstract

Logic programming is expected to make knowledge information processing feasible. However, conventional Prolog systems lack both processing power and flexibility for solving large problems. To overcome these limitations, an approach is developed in which natural execution features of logic programs can be represented using Proof Diagrams. AND/ OR parallel processing based on a goal-rewriting model is examined. Then the abstract architecture of a highly parallel inference engine (PIE) is described. PIE makes it possible to achieve logic/control separation in machine architecture. The architecture proposed here is discussed from the viewpoint of its high degree of parallelism and flexibility in problem solving in comparison with other approaches.

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Authors and Affiliations

  1. Department of Electrical Engineering, Faculty of Engineering, The University of Tokyo, 3-1 Hongo 7-chome, Bunkyo-ku, 113, Tokyo, Japan

    Atsuhiro Goto, Hidehiko Tanaka & Tohru Moto-Oka

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  1. Atsuhiro Goto
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  2. Hidehiko Tanaka
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  3. Tohru Moto-Oka
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Goto, A., Tanaka, H. & Moto-Oka, T. Highly parallel inference engine PIE —Goal rewriting model and machine architecture—. NGCO 2, 37–58 (1984). https://doi.org/10.1007/BF03037051

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  • DOI: https://doi.org/10.1007/BF03037051

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