Abstract
The problems of testing mixed-signal circuits are becoming increasingly intractable as circuit density and functionality increase. The most urgent of these problems is seen as the ability to perform interconnect testing without the need for physical probing. A structured approach, in which test circuitry is incorporated into the chip in order to provide access for board test, was proposed in an earlier paper: an improved version of this structure, which is compatible with the established digital Standard 1149.1, is described and evaluated using SPICE simulation.
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References
IEEE Standard 1149.1: Standard Test Access Port and Boundary-Scan Architecture, IEEE Computer Society, 1990.
B.R. Wilkins, “A structure for board-level mixed-signal testability,”Proc. ITC, 556–557, 1992.
P.T. Wagner, “Interconnect testing with boundary scan,”Proc. ITC, 52–57, 1987.
P.J. Dickinson, and B.R. Wilkins, “Interconnect testing for busstructured systems,”Proc. ETC, 476–483, 1993.
B.R. Wilkins, S. Oresjo, and B.S. Suparjo, “Towards a mixed-signal testability bus standard: P1149.4,”Proc. ETC, 58–65, 1993.
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Wilkins, B.R., Suparjo, B.S. A structure for interconnect testing on mixed-signal boards. J Electron Test 4, 369–374 (1993). https://doi.org/10.1007/BF00972161
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DOI: https://doi.org/10.1007/BF00972161