Abstract
It is shown that a cascade of carry-free serial-parallel multipliers, fed by bit-serial samples with no separation between successive samples (i.e., with maximum sampling rate for a given bit rate), produces one convolution value everyp withp>1. This circuit is called aphase-convolver, and it is shown that a full convolver can be obtained by associatingp phase convolvers (polyphase convolver). Under some assumptions, a polyphase convolver can be implemented as a stack of bit-slices. It appears possible to program, by means of variables stored in a register, a slices-pack in order to obtain a convolver for a prescribed number of convolution terms and of weights and samples lengths. It is also possible to by-pass a faulty slice (or a group of slices) by means of variables stored in a second register.
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Dadda, L. A polyphase architecture for serial-input convolvers. J VLSI Sign Process Syst Sign Image Video Technol 2, 17–27 (1990). https://doi.org/10.1007/BF00931033
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DOI: https://doi.org/10.1007/BF00931033