Abstract
Low Voltage Differential Signaling (LVDS) driver is used for high data rate transmission for chip to chip, circuit board to circuit board through copper cables or through circuit board metal tracks. This is a backbone of high speed transmission specified by EIA/IEEE standard. This driver circuit is designed in 0.18 \(\upmu \)m CMOS technology and can transmit at data rate of 1.25 Gbps. It requires single power supply of 3.3 V. This design has common mode feedback circuit (CMFB) with fast settling time. This feature improves the data communication where there is a change of common mode voltage or power switching taking place frequently. The silicon Area required by this design is 0.034 mm\(^2\). This design can be used in I/O pad, for serializer application etc. and can be easily ported to lower geometry technology.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
IEEE standard for low-voltage differential signals (LVDS) for scalable coherent interface (SCI) 1596(3)
TIA-644, Revision A, February 2001—Electrical characteristics of low voltage differential signaling (LVDS) interface circuits
Mandal G, Mandal P (2004) Low power LVDS transmitter with low common mode variation for 1 Gb/s-per pin operation. Proc ISCAS I:1120–1123
Boni A, Pierazzi A, Vecchi D (1994) LVDS 1, 0 interface for Gb, s-per-pin operation in 0.35-pm CMOS. IEEE J Solid-State Circuit 36(4):706–711. SCI-LVDS Standard (1996) IEEE Std 1596(3)
Jacob R (2009) CMOS circuit design, layout and simulation, 2nd edn. IEEE Press, Piscataway
Tajalli A, Leblebici Y (2009) A slew controlled LVDS output driver circuit in 0.18 um CMOS technology. IEEE J Solid State Circuits 44(2)
Wang C, Huang J, Huang J (2004) 1.0 Gbps LVDS transceiver design for LCD panel. In: Advanced system integrated circuits IEEE Asia-Pacific conference
Sansen Willy MC (2006) Analog design essentials. Springer, Dordrecht
Chen M et al (2005) Low-voltage low-power LVDS driver. IEEE J Solid-State Circuit 40(2):472–479
Jamasb S, Jalilizeinali R, Chau P (2001) A 622 MHz stand-alone LVDS driver pad in 0.18 \(\upmu \)m CMOS. In: Proceedings of the 44th IEEE 2001 midwest symposium on circuits and systems, vol 2, pp 610–613
Bratov V, Binkley J, Katzman V, Choma J (2005) Architecture and implementation of a low-power LVDS output buffer for high-speed applications. IEEE Trans Circuits Syst I: Reg Pap 53(10):2101–2108
Gabara T, Fischer W, Werner W, Siegel S, Kothandaraman M, Metz P, Gradl D (1997) LVDS I/O buffers with a controlled reference circuit. In: ASIC conference and exhibit proceedings tenth annual IEEE international
Razavi B (2002) Design of analog CMOS integrated circuit
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Malik, M., Prakash, N.R., Kumar, A., Kaur, J. (2023). High Speed LVDS Driver Design with Fast Settling Common Mode Feedback Circuit. In: Nagaria, R.K., Tripathi, V.S., Zamarreno, C.R., Prajapati, Y.K. (eds) VLSI, Communication and Signal Processing. VCAS 2022. Lecture Notes in Electrical Engineering, vol 1024. Springer, Singapore. https://doi.org/10.1007/978-981-99-0973-5_11
Download citation
DOI: https://doi.org/10.1007/978-981-99-0973-5_11
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-99-0972-8
Online ISBN: 978-981-99-0973-5
eBook Packages: EngineeringEngineering (R0)