Abstract
QCA is a transistor-free method of realizing nanoscale circuit architectures. When compared to the commonly utilized CMOS technology, QCA circuits perform faster, more dense, and consume less energy. In this study, a new digital comparator structure based on QCA nanotechnology is suggested. The digital comparator, that contains 2 binary integers, is a fundamental and crucial module of the CPU. As compared to previous designs, the suggested digital comparator is optimum, single-layered, and contains less QCA cells. The suggested digital comparator has been evaluated to current digital comparators for several performance parameters. The suggested coplanar comparator has been built using the smallest QCA cells possible, resulting in a smaller total cell area and total coverage area. As a result of the low dissipation of energy for the suggested design, the suggested digital comparator becomes extremely energy efficient.
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Syamala Devi, P., Vaniha, K., Vidya Sagar, K., Vinitha, P., Sumanth Kumar, K. (2023). Design of QCA-Based 1-Bit Magnitude Comparator. In: Kumar, A., Senatore, S., Gunjan, V.K. (eds) ICDSMLA 2021. Lecture Notes in Electrical Engineering, vol 947. Springer, Singapore. https://doi.org/10.1007/978-981-19-5936-3_77
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DOI: https://doi.org/10.1007/978-981-19-5936-3_77
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