Skip to main content
SpringerLink
Log in

Soft Computing Approach for VLSI Mincut Partitioning: The State of the Arts

  • Conference paper
  • First Online:
Book cover Proceedings of the Second International Conference on Soft Computing for Problem Solving (SocProS 2012), December 28-30, 2012

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 236))

  • 1159 Accesses

Abstract

Recent research shows that the partitioning of VLSI-based system plays a very important role in embedded system designing. There are several partitioning problems that can be solved at all levels of VLSI system design. Moreover, rapid growth of VLSI circuit size and its complexity attract the researcher to design various efficient partitioning algorithms using soft computing approaches. In VLSI netlist is used to optimize the parameters like mincut, power consumption, delay, cost, and area of the partitions. Hence, the Genetic Algorithm is a soft computational meta-heuristic method that has been applied to optimize these parameters over the past two decades. Here in this paper, we have summarized important schemes that have been adopted in Genetic Algorithm for optimizing one particular parameter, called mincut, to solve the partitioning problem.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 259.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 329.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Johannes, F.M.: Partitioning of VLSI circuits and systems. In: Proceedings 33rd ACM/IEEE International Conference on Design Automation, pp. 83–87 (1996).

    Google Scholar 

  2. Mazumder, P., Rudnick, E.M.: Genetic Algorithms for VLSI Design, Layout and Test Automation Partitioning. Prentice Hall, New Jercy (1999)

    Google Scholar 

  3. Nan, G.F., Li, M.Q., Kou, J.S.: Two novel encoding strategies based genetic algorithms for circuit partitioning. In: Proceedings of 3rd International Conference on Machine Learning and, Cybernetics 4, pp. 2182–2188 (2004).

    Google Scholar 

  4. Sherwani, N.: Algorithms for VLSI Physical Design and Automation, 3rd edn. New Delhi, Springer (India) Private Limited (2005)

    Google Scholar 

  5. Bui, T.N., Moon, B.R.: A fast and stable hybrid genetic algorithm for the ratio-cut partitioning problem on hypergraphs. In: proceedings of 31st ACM/IEEE International Conference on Design Automation, pp. 664–669 (1994).

    Google Scholar 

  6. Tan, X., Tong, J., Tan, P., Park, N., Lombardi, F.: An efficient multi-way algorithm for balance partitioning of VLSI Circuits. In: Proceedings of International IEEE Conference on Computer Design: VLSI in Computers and Processors, pp. 608–613 (1997).

    Google Scholar 

  7. Sanchis, L.A.: Multiple-way network partitioning with different cost functions. IEEE Trans. Comput. 42(12), 1500–1504 (1993)

    Article  Google Scholar 

  8. Alpert, C.J.: The ISPD98 circuit benchmark suite. In: Proceedings of International Symposium on Physical Design, pp. 80–85 (1998).

    Google Scholar 

  9. Alpert, C.J., Khang, A.B.: Recent directions in netlist partitioning: a survey. Integr. VLSI J. 19(1–2), 1–81 (1995)

    Article  MATH  Google Scholar 

  10. Krishnamurthy, B.: An improved min-cut algorithm for partitioning VLSI networks. IEEE Trans. Comput 33(5), 438–446 (1984)

    Article  MATH  MathSciNet  Google Scholar 

  11. Bui, T.N., Moon, B.R.: Genetic algorithm and graph partitioning. IEEE Trans. Comput. 45(7), 841–855 (1996)

    Article  MATH  MathSciNet  Google Scholar 

  12. Andreev, K., Racke, H.: Balanced graph partitioning. In: Proceedings of 16th International Annual ACM Symposium on Parallelism in Algorithms and Architectures, pp. 120–124 (2004).

    Google Scholar 

  13. Gill, S.S., Chandel, R., Chandel, A.: Genetic algorithm based approach to circuit partitioning. Int. J. Comput. Electr. Eng. 2(2), 196–201 (2010)

    Article  Google Scholar 

  14. Chambers, L.D.: Practical Handbook of Genetic Algorithms. CRC Press, Inc. Boca Raton(1995).

    Google Scholar 

  15. Jiang, X., Shen, X., Zhang, T., Liu, H.: An improved circuit-partitioning algorithm based on min-cut equivalence relation. Integr. VLSI J. 36(1–2), 55–68 (2003)

    Article  Google Scholar 

  16. Alpert, C.J., Huang, J.H., Khang, A.B.: Multilevel circuit partitioning. In: proceedings of 34th ACM/IEEE International Conference on Design Automation, pp. 530–533 (1997).

    Google Scholar 

  17. Fiduccia, C.M., Mattheyses, R.M.: A linear time heuristic for improving network partitions. In: Proceedings of 19th International Conference on Design Automation, pp. 175–181 (1982).

    Google Scholar 

  18. Yang, H., Wong, D.F.: Efficient network flow based min-cut balanced partitioning. Proceedings of IEEE/ACM International Conference on Computer-Aided Design 15(12), 1533–1540 (1996)

    Google Scholar 

  19. Liu, H., Wong, D.F.: Network-flow-based multiway partitioning with area and pin constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1), 50–59 (1998)

    Article  Google Scholar 

  20. Slowik, A., Bialko, M.: Partitioning of VLSI circuits on subcircuits with minimal number of connections using evolutionary algorithm. In: Proceedings of International Conference AISC, pp. 470–478(2006).

    Google Scholar 

  21. Goldberg, D.E., Lingle, R.,: Alleles, loci and the TSP. In: Proceedings of International Conference on Genetic Algorithms, pp. 154–159 (1985).

    Google Scholar 

  22. Gill, S.S., Chandel, R., Chandel, A.: Comparative study of ant colony and genetic algorithms for VLSI circuit partitioning. Eng. Tech. 28, 890–894 (2009)

    Google Scholar 

  23. Sait, S.M., El-Maleh, A.H., Al-Abaji, R.H.: Evolutionary algorithms for VLSI multi-objective netlist partitioning. Eng. Appl. Artif. Intell. 19(3), 257–268 (2005)

    Article  Google Scholar 

  24. Peng, S., Chen, G.L., Guo, W.Z.: A discrete PSO for partitioning in VLSI circuit. In: Proceedings of International Conference on Computational Intelligence and, Software Engineering, pp. 1–4 (2009).

    Google Scholar 

  25. Kolar, D., Puksec, J.D., Branica, I.: VLSI circuit partitioning using simulated annealing algorithm. In: Proceedings of IEEE Melecon, pp. 12–15 (2004).

    Google Scholar 

  26. Lodha, S.K., Bhatia, D.: Bipartitioning circuits using TABU search. In: Proceedings of 11th IEEE Annual International Conference on ASIC, pp. 223–227 (1998).

    Google Scholar 

  27. Rajaraman, R., Wong, D.F.: Optimal clustering for delay minimization. In: Proceedings of 30th ACM/IEEE International Conference on Design Automation, pp. 309–314 (1993).

    Google Scholar 

  28. Yang, H., Wong, D.F.: Circuit clustering for delay minimization under area and pin constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9), 976–986 (1997)

    Article  Google Scholar 

  29. Vaishnav, H., Pedram, M.: Delay optimal partitioning targeting low power VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6), 298–301 (1999)

    Article  Google Scholar 

  30. Yang, H., Wong, D.F.: Optimal min-area min-cut replication in partitioned circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11), 1175–1183 (1998)

    Article  Google Scholar 

  31. Kim, C.K., Moon, B.R.: Dynamic embedding for genetic VLSI circuit partitioning. Eng. Appl. Artif. Intell. 11(1), 67–76 (1998)

    Article  Google Scholar 

  32. Esbensen, H., Mazumder, P.: SAGA: A unification of the genetic algorithm with simulated annealing and its applictaion to macro-cell placement. In: Proceedings of 7th International Conference on, VLSI Design, pp. 211–214 (1992).

    Google Scholar 

  33. Cohoon, J.P., Hegde, S.E., Martin, W.N., Richards, D.S.: Distributed genetic algorithms for the floorplan design problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4), 483–492 (1991)

    Article  Google Scholar 

  34. Lienig, J., Thulasiraman, K.: A genetic algorithm for channel routing in VLSI circuits. Evol. Comput. 1(4), 293–311 (1993)

    Article  Google Scholar 

  35. Schnecke, V., Vornberger, O.: An adaptive parallel genetic algorithm for VLSI layout optimization. In: Proceedings of 4th International Conference on Parallel Problem Solving from Nature III, pp. 859–868 (1996).

    Google Scholar 

  36. Maulik, U., Saha, I.: Modified differential evolution based fuzzy clustering for pixel classification in remote sensing imagery. Pattern Recognit. 42(9), 2135–2149 (2009)

    Article  MATH  Google Scholar 

  37. Saha, I., Maulik, U., Plewczynski, D.: A new multi-objective technique for differential fuzzy clustering. Appl. Soft Comput. 11(2), 2765–2776 (2011)

    Article  Google Scholar 

Download references

Acknowledgments

Mr. Saha is grateful to the All India Council for Technical Education (AICTE) for providing National Doctoral Fellowship (NDF) to support the work.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, MCKV Institute of Engineering, Howrah, Liluah, 711204, India

    Debasree Maity

  2. Department of Computer Science and Engineering, Jadavpur University, Kolkata, 700032, India

    Indrajit Saha & Ujjwal Maulik

  3. Interdisciplinary Centre for Mathematical and Computational Modelling, University of Warsaw, 02106, Warsaw, Poland

    Dariusz Plewczynski

Authors
  1. Debasree Maity
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Indrajit Saha
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Ujjwal Maulik
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Dariusz Plewczynski
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Indrajit Saha .

Editor information

Editors and Affiliations

  1. Institute of Engineering and Technology, JK Lakshmipat University, Jaipur, Rajasthan, India

    B. V. Babu

  2. Department of Computer Science, Liverpool Hope University, Liverpool, United Kingdom

    Atulya Nagar

  3. Department of Mathematics, Indian Institute of Technology Roorkee, Roorkee, Uttarakhand, India

    Kusum Deep

  4. Department of Paper Technology, Indian Institute of Technology Roorkee, Roorkee, India

    Millie Pant

  5. Department of Applied Mathematics, South Asian University, New Delhi, India

    Jagdish Chand Bansal

  6. Institute of Engineering and Technology, JK Lakshmipat University, Jaipur, Rajasthan, India

    Kanad Ray

  7. Institute of Engineering and Technology, JK Lakshmipat University, Jaipur, Rajasthan, India

    Umesh Gupta

Rights and permissions

Reprints and permissions

Copyright information

© 2014 Springer India

About this paper

Cite this paper

Maity, D., Saha, I., Maulik, U., Plewczynski, D. (2014). Soft Computing Approach for VLSI Mincut Partitioning: The State of the Arts. In: Babu, B., et al. Proceedings of the Second International Conference on Soft Computing for Problem Solving (SocProS 2012), December 28-30, 2012. Advances in Intelligent Systems and Computing, vol 236. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1602-5_95

Download citation

  • DOI: https://doi.org/10.1007/978-81-322-1602-5_95

  • Published:

  • Publisher Name: Springer, New Delhi

  • Print ISBN: 978-81-322-1601-8

  • Online ISBN: 978-81-322-1602-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation