Abstract
Power dissipation has become a prime constraint in high performance applications, especially in clocked devices like microprocessor and portable devices. Optimizations for the ASIC cells are crucial in order to improve the performance of various low power and high performance devices. The design criterion of primitive cells is usually multi-fold. Optimization of several devices for speed and power is a significant issue in low-voltage and low-power applications. These issues can be overcome by incorporating Gated Diffusion Input (GDI) technique. This paper mainly presents the design of primitive cells like AND, OR, NAND, NOR, MUX, XOR and XNOR cell in Modified Gate Diffusion Input Technique. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. Delay and power has been evaluated by Tanner simulator using TSMC 0.250 technologies considering minimum power design. The simulation results reveal better delay and power performance of proposed primitive cells as compared to existing GDI cell and CMOS at 0.250μm CMOS technologies.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Agrawal, A.K., Wairya, S., Nagaria, R.K., Tiwari, S.: A New Mixed Gate Diffusion Input Full Adder Topology for High Speed Low Power Digital Circuits. World Applied Sciences Journal (Special Issue of Computer & IT) 7, 138–144 (2009)
Zimmermann, R., Fichtner, W.: Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circuits 32, 1079–1090 (1997)
Calhoun, B., Cao, Y., Li, X., Mai, K., Pileggi, L., Rutenbar, R., Shepard, K.: Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proceedings of the IEEE 96(2), 343–365 (2008)
Al-Assadi, W., Jayasumana, A.P., Malaiya, Y.K.: Pass-transistor logic design. Int. J. Electron. 70, 739–749 (1991)
Morgenshtein, A., Fish, A., Wagner, I.A.: Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(5) (October 2002)
Uma, R., Dhavachelvan, P.: Performance of Full Adders with Skewed Logic. In: International Conference on Advances in Computing and Communications, ACC 2012 (2012)
Balasubramanian, P., John, J.: Low Power Digital design using modified GDI method. IEEE (2006)
Uma, R., Dhavachelvan, P.: Analysis on Impact of Behavioral Modeling in Performance of Synthesis Process. In: Third International workshop on VLSI, VLSI 2012 (2012)
Uma, R., Dhavachelvan, P.: Performance of Adders with Logical Optimization in FPGA. In: First Interantional Conference on Signal, Image Processing and Pattern Recognition, SPRR 2012 (2012)
Morgenshtein, A., Shwartz, I., Fish, A.: Gate Diffusion Input (GDI) Logic in Standard CMOS Nanoscale Process. In: 2010 IEEE 26th Convention of Electrical and Electronics Engineers in Israel (2010)
Agrawal, A.K., Mishra, S., Nagaria, R.K.: Proposing a Novel Low-Power High-Speed Mixed GDI Full Adder Topology. IEEE (2010)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer India
About this paper
Cite this paper
Uma, R., Dhavachelvan, P. (2013). ASIC Primitive Cells in Modified Gated Diffusion Input Technique. In: Kumar M., A., R., S., Kumar, T. (eds) Proceedings of International Conference on Advances in Computing. Advances in Intelligent Systems and Computing, vol 174. Springer, New Delhi. https://doi.org/10.1007/978-81-322-0740-5_57
Download citation
DOI: https://doi.org/10.1007/978-81-322-0740-5_57
Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-0739-9
Online ISBN: 978-81-322-0740-5
eBook Packages: EngineeringEngineering (R0)