Abstract
In this paper we describe the design and implementation of a reconfigurable instruction systolic array. Its redundant interconnection structure allows for a very flexible reconfiguration of the array in the presence of faulty processing elements in order to utilize as many fault-free processing elements as possible. Two strategies are described for configuring the array under the constraint of a limited physical distance between logical neighbors.
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© 1991 Springer-Verlag Berlin Heidelberg
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Phieler, M., Schimmler, M., Schmeck, H. (1991). A Reconfigurable Instruction Systolic Array. In: Cin, M.D., Hohl, W. (eds) Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 283. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-76930-6_26
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DOI: https://doi.org/10.1007/978-3-642-76930-6_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-54545-3
Online ISBN: 978-3-642-76930-6
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