Abstract
Nowadays highly competitive market of consumer electronics is very sensitive to the time it takes to introduce a new product. However, the ever-growing complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging. In ASIPs, it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corner cases in a defined time schedule. As a consequence, the gap between the proposed verification plan and the quality of verification tasks is widening due to this time restriction. One way how to solve this issue is using faster, efficient and cost-effective methods of verification. The aim of this paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and is robust enough to detect also well-hidden bugs.
This work was supported by the European Social Fund (ESF) in the project Excellent Young Researchers at BUT (CZ.1.07/2.3.00/30.0039), the IT4Innovations Centre of Excellence (CZ.1.05/1.1.00/02.0070), Brno Ph.D. Talent Scholarship Programme, the BUT FIT project FIT-S-11-1, research plan no. MSM0021630528, and the research funding MPO ČR no. FR-TI1/038.
Chapter PDF
References
Fauth, A., Van Praet, J., Freericks, M.: Describing instruction set processors using nML. In: Proceedings of European Design and Test Conference, Paris, pp. 503–507 (1995) ISBN 0-8186-7039-8
Hoffmann, A., Meyr, H., Leupers, R.: Architecture Exploration for Embedded Processors with LISA. Springer (2002) ISBN 1402073380
Codasip Framework. Codasip (2012), http://www.codasip.com/
Martin, G., Bailey, B., Piziali, A.: ESL Design and Verification: A Prescription for Electronic System Level Methodology (Systems on Silicon). Morgan Kaufmann (2007) ISBN 0123735513
Mentor Graphics Verification Academy. UVM/OVM (2012), https://verificationacademy.com/topics/verification-methodology
Mishra, P., Dutt, N.: Processor Description Languages (Systems on Silicon), vol. 1. Morgan Kaufmann (2008) ISBN 9780123742872
Paradigm Works SystemVerilog Frameworks Template Generator (2012), http://svf-tg.paradigm-works.com/svftg/
Processor Designer (2012), http://www.synopsys.com/Systems/BlockDesign/ProcessorDev/Pages/default.aspx
Azevedo, R., et al.: The ArchC architecture description language and tools. International Journal of Parallel Program 33(5), 453–484 (2005) ISSN 0885-7458
Synopsys. Pioneer NTB (2012), http://www.synopsys.com/Tools/Verification/FunctionalVerification/Pages/Pioneer-NTB.aspx
SystemC Project (2012), http://www.systemc.org/home/
Target (2012), http://www.retarget.com/
The LLVM Compiler Infrastructure Project (2012), http://llvm.org/
Přikryl, Z.: Advanced Methods of Microprocessor Simulation. Information Sciences and Technologies, Bulletin of the ACM Slovakia 3(3), 1–13 (2011) ISSN 1338-1237
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 IFIP International Federation for Information Processing
About this paper
Cite this paper
Šimková, M., Přikryl, Z., Kotásek, Z., Hruška, T. (2013). Automated Functional Verification of Application Specific Instruction-set Processors. In: Schirner, G., Götz, M., Rettberg, A., Zanella, M.C., Rammig, F.J. (eds) Embedded Systems: Design, Analysis and Verification. IESS 2013. IFIP Advances in Information and Communication Technology, vol 403. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-38853-8_12
Download citation
DOI: https://doi.org/10.1007/978-3-642-38853-8_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-38852-1
Online ISBN: 978-3-642-38853-8
eBook Packages: Computer ScienceComputer Science (R0)