Abstract
Fault tolerance network demands the router provide graceful degradation in the presence of faults such as a noisy high-speed serial lane that causes excessive retransmissions. Auto-degrade network links dynamically map out a faulty lane and keep operating, albeit at a lower bandwidth. In this paper we design a Frame Error Rate Testing (FERT) circuit at link-level in order to prevent the use of a faulty link. We show the design and implementation of frame error rate testing circuit operating at line speed. Furthermore we describe the fault tolerance mechanism at link layer using frame error rate testing. We also present and evaluate the power and logic cost of the ASIC based as well as FPGA based FERT implementation.
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© 2012 Springer-Verlag Berlin Heidelberg
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Dai, Y., Wang, Kf., Xu, Wx., Zhang, Hy., Wang, Sg. (2012). Frame Error Rate Testing for High Speed Optical Interconnect. In: Xiang, Y., Stojmenovic, I., Apduhan, B.O., Wang, G., Nakano, K., Zomaya, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2012. Lecture Notes in Computer Science, vol 7440. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33065-0_4
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DOI: https://doi.org/10.1007/978-3-642-33065-0_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-33064-3
Online ISBN: 978-3-642-33065-0
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