Abstract
This chapter discusses the use of hybrid continuous-time /discrete-time fourth-order cascade two-stage 2-2 ΣΔ modulators for wideband low-power wireless applications. The modulator architecture under study is based on a new concept of multi-rate operation, in which the front-end stage – implemented using continuous-time (Gm-C) integrators – operates at a higher rate than the back-end (switched-capacitor) stage. This strategy benefits from the faster operation of continuous-time circuits while keeping power efficiency and high robustness against circuit element tolerances. A comparison with conventional multi-rate and single-rate (continuous-time) ΣΔ modulators is carried out based on the impact of main circuit-level error mechanisms, namely: mismatch, finite OTA dc gain and finite gain-bandwidth product. Closed-form analytical expressions are derived for the nonideal in-band noise power of the different architectures under study, demonstrating a good agreement with simulations and showing the benefits of the presented approach. Simulation results show that the proposed modulator is able to operate with a maximum sampling rate of up to 1GHz, digitizing signals with a 44-to-92dB peak signal-to-(noise+distortion) ratio within a programmable 5-to-60MHz bandwidth.
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García-Sánchez, J.G., de la Rosa, J.M. (2012). Efficient Multi-rate Hybrid Continuous-Time/Discrete-Time Cascade 2-2 Sigma-Delta Modulators for Wideband Telecom. In: Mir, S., Tsui, CY., Reis, R., Choy, O.C.S. (eds) VLSI-SoC: Advanced Research for Systems on Chip. VLSI-SoC 2011. IFIP Advances in Information and Communication Technology, vol 379. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32770-4_8
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