Abstract
In this paper, we design and analyze two asynchronous circuits: 1) a simple micropipeline and 2) an asynchronous MIPS processor. We use a commercially available 65 nm Virtex-5 FPGA device for those two designs. The asynchronous FIFO implemented on the Virtex-5 device shows 452 MHz throughput at the simulation under the worst case operating condition. The micropipeline is extended to incorporate a conventional 5-stage pipelined MIPS datapath. Our asynchronous MIPS processor works successfully on the Virtex-5 FPGA device without a clock source, crystal oscillator, and 53.2 MHz throughput is measured.
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Lee, SJ., Lee, DY., Ko, YW., Lee, JG. (2012). Asynchronous Circuit Design on an FPGA: MIPS Processor Case Study. In: Lee, G., Howard, D., Ślęzak, D., Hong, Y.S. (eds) Convergence and Hybrid Information Technology. ICHIT 2012. Communications in Computer and Information Science, vol 310. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32692-9_60
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DOI: https://doi.org/10.1007/978-3-642-32692-9_60
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-32691-2
Online ISBN: 978-3-642-32692-9
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