Abstract
Coarse-grained reconfigurable architecture (CGRA) brings more powerful performance than the traditional CPU-like architecture. In this paper, we proposed a fast and effective domain-specific design method for function units of a CGRA named ProDFA. The proposed design method mainly concludes a top-down subgraph enumeration algorithm and a heuristic subgraph identification process based on topological searching. We used a clustering technique to accelerate the maximal valid subgraph enumeration (MVSE), and for the first time the top-down MVSE is combined with the identification process through the topological ordering. Candidate convex subgraphs are finally grouped into function sets according to their isomorphism. Experimental result shows that the performance of subgraph enumeration is improved in most cases, and a small number of candidate function sets are identified.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Lee, M.H., Singh, H., Lu, G.M., Bagherzadeh, N., et al.: Design and Implementation of the MorphoSys Reconfigurable Computing Processor. J. VLSI Signal Process. Syst, 147–164 (2000)
Goldstein, S.C., Schmit, H., Moe, M., Budiu, M., et al.: PipeRench: a co/processor for streaming multimedia acceleration. In: ISCA 1999: Proceedings of the 26th Annual International Symposium on Computer Architecture, pp. 28–39 (1999)
Mei, B., Vernalde, S., Verkest, D., Man, H.D., Lauwereins, R.: ADRES An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Recon?gurable Matrix. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 61–70. Springer, Heidelberg (2003)
Khawam, S., Nousias, I., Milward, M., Yi, Y., Muir, M., Arslan, T.: The Reconfigurable Instruction Cell Array. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16(1), 75–85 (2008)
Kastner, R., Bozorgzadeh, E.: Instruction Generation for Hybrid Reconfigurable Systems. ACM Transactions on Design Automation of Electronic Systems 7(4), 605–627 (2002)
Atasu, K., Pozzi, L., Ienne, P.: Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints. In: DAC 2003, pp. 1–6 (2003)
Clark, N., Zhong, H., Mahlke, S.: Automated Custom Instruction Generation for Domain-Specific Processor Acceleration. IEEE Transactions on Computer 54(10), 1258–1271 (2005)
Pozzi, L., Atasu, K., Ienne, P.: Exact and Approximate Algorithms for the Extension of Embedded Processor Instruction Sets. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems 25(7), 1209–1230 (2006)
Pothineni, N., Kumar, A., Paul, K.: Application Specific Datapath Extension with Distributed I/O Functional Units. In: 20th VLSI Design - 6th Embedded Systems, pp. 551–556 (2007)
Bonzini, P., Pozzi, L.: Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension. In: DATE 2007, pp. 1331–1336 (2007)
Chen, X., Maskell, D.L., Sun, Y.: Fast Identification of Custom Instructions for Extensible Processors. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 26(2), 359–368 (2007)
Atasu, K., Ozturan, C., Dundar, G., Mencer, O., Luk, W.: CHIPS: Custom hardware instruction processor synthesis. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 27(3), 528–541 (2008)
Verma, A.K., Brisk, P., Ienne, P.: Fast, quasi-optimal, and pipelined instruction-set extensions. In: Proceedings of the 2008 Asia and South Pacific Design Automation Conference, pp. 334–339 (2008)
Atasu, K., Mencer, O., Luk, W., Ozturan, C.: Fast Custom Instruction Identification by Convex Subgraph Enumeration. In: ASAP 2008, pp. 1–6 (2008)
Li, T., Sun, Z., Jigang, W., Lu, X.: Fast Enumeration of Maximal Valid Subgraphs for Custom-instruction Identification. In: CASES 2009, pp. 1–8 (2009)
Lam, S.-K., Srikanthan, T.: Rapid design of area-efficient custom instructions for reconfigurable embedded processing. Journal of Systems Architecture 55, 1–14 (2009)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Yan, M., Yang, Z., Yang, L., Liu, L., Li, S. (2011). Practical and Effective Domain-Specific Function Unit Design for CGRA. In: Murgante, B., Gervasi, O., Iglesias, A., Taniar, D., Apduhan, B.O. (eds) Computational Science and Its Applications - ICCSA 2011. ICCSA 2011. Lecture Notes in Computer Science, vol 6786. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21934-4_47
Download citation
DOI: https://doi.org/10.1007/978-3-642-21934-4_47
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-21933-7
Online ISBN: 978-3-642-21934-4
eBook Packages: Computer ScienceComputer Science (R0)