Abstract
This article presents a project of an embedded system realized on a programmable matrix. The main element is a reconfigurable processor of MIPS architecture. It was implemented in the VHDL in such way that its instruction set can be reduced to the set of instructions present in the program memory. As the result a processor will contain the logic that is absolutely necessary. This solution yields a device that requires fewer gates to be synthesized in the programmable matrix and has a potential to increase the speed of the information processing performed by the system in the target FPGA.
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Ziębiński, A., Świerc, S. (2009). The VHDL Implementation of Reconfigurable MIPS Processor. In: Cyran, K.A., Kozielski, S., Peters, J.F., Stańczyk, U., Wakulicz-Deja, A. (eds) Man-Machine Interactions. Advances in Intelligent and Soft Computing, vol 59. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-00563-3_69
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DOI: https://doi.org/10.1007/978-3-642-00563-3_69
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-00562-6
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