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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings

  • Conference proceedings
  • © 2007

Overview

Editors:
  1. Nadine Azémard
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  2. Lars Svensson
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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 4644)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: PATMOS 2007.

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Table of contents (60 papers)

  1. Front Matter

    Download chapter PDF

  2. Session 1 - High-Level Design (1)

    1. System-Level Application-Specific NoC Design for Network and Multimedia Applications

      • Lazaros Papadopoulos, Dimitrios Soudris
      Pages 1-9

    2. Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements

      • Nicolas Fournel, Antoine Fraboulet, Paul Feautrier
      Pages 10-19

    3. A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms

      • Ioannis Panagopoulos, Christos Pavlatos, George Manis, George Papakonstantinou
      Pages 20-30

    4. An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture

      • Julien Delorme
      Pages 31-42

  3. Session 2 - Low Power Design Techniques

    1. Template Vertical Dictionary-Based Program Compression Scheme on the TTA

      • Lai Mingche, Wang Zhiying, Guo JianJun, Dai Kui, Shen Li
      Pages 43-52

    2. Asynchronous Functional Coupling for Low Power Sensor Network Processors

      • Delong Shang, Chihoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeonghoon Oh et al.
      Pages 53-63

    3. A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs

      • Noureddine Chabini
      Pages 64-74

    4. Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports

      • Saleh Abdel-Hafeez, Shadi M. Harb, William R. Eisenstadt
      Pages 75-85

    5. The Design and Implementation of a Power Efficient Embedded SRAM

      • Yijun Liu, Pinghua Chen, Wenyan Wang, Zhenkun Li
      Pages 86-96

  4. Session 3 - Low Power Analog Circuits

    1. Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN

      • Björn Lipka, Ulrich Kleine
      Pages 97-106

    2. Settling Time Minimization of Operational Amplifiers

      • Andrea Pugliese, Gregorio Cappuccino, Giuseppe Cocorullo
      Pages 107-116

    3. Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs

      • Cosmin Popa
      Pages 117-124

  5. Session 4 - Statistical Static Timing Analysis

    1. Computation of Joint Timing Yield of Sequential Networks Considering Process Variations

      • Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma Vrudhula
      Pages 125-137

    2. A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation

      • V. Migairou, R. Wilson, S. Engels, Z. Wu, N. Azemard, P. Maurine
      Pages 138-147

    3. A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits

      • Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong R. Jiang, Yao-Wen Chang
      Pages 148-159

  6. Session 5 - Power Modeling and Optimization

    1. A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect

      • Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie
      Pages 160-170

    2. Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components

      • Marko Hoyer, Domenik Helms, Wolfgang Nebel
      Pages 171-180

    3. Logic Style Comparison for Ultra Low Power Operation in 65nm Technology

      • Mandeep Singh, Christophe Giacomotto, Bart Zeydel, Vojin Oklobdzija
      Pages 181-190

    4. Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation

      • CR. Parthasarathy, A. Bravaix, C. Guérin, M. Denais, V. Huard
      Pages 191-200
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  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

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About this book

th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.

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